gpu: nvgpu: Add CDE bits in FECS header

In case of CDE channel, T1 (Tex) unit needs to be promoted to 128B
aligned, otherwise causes a HW deadlock. Gpu driver makes changes in
FECS header which FECS uses to configure the T1 promotions to aligned
128B accesses.

Bug 200096226

Change-Id: Ic006b2c7035bbeabe1081aeed968a6c6d11f9995
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/802327
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

1 files changed, 12 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
index cefd91e1..34f8a6a4 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_ctxsw_prog_gm20b.h
@@ -58,6 +58,18 @@ static inline u32 ctxsw_prog_main_image_num_gpcs_o(void)
 {
         return 0x00000008;
 }
+static inline u32 ctxsw_prog_main_image_ctl_o(void)
+{
+        return 0x0000000c;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_enabled_f(void)
+{
+        return 0x400;
+}
+static inline u32 ctxsw_prog_main_image_ctl_cde_disabled_f(void)
+{
+        return 0x0;
+}
 static inline u32 ctxsw_prog_main_image_patch_count_o(void)
 {
         return 0x00000010;