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authorTerje Bergstrom <tbergstrom@nvidia.com>2016-05-13 10:56:43 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-05-18 11:15:11 -0400
commit67a41e46a230cde7353e4cd46040f1e71d7cd289 (patch)
tree0697ce5ba224db6a92cdab0b192a8069f669be63 /drivers/gpu/nvgpu/gm20b
parent8f48afe26bc39fd7508646e8c3ea6bfeb665beae (diff)
gpu: nvgpu: Read all fields of device_info
We were not using the engine_type field in device info, and the code did not handle chained entries properly. The code assumed that first entry is for graphics and second for CE, which is not always true. Improve the code to go through all entries of device_info, and preserve values across entries until we reach the last entry. Only last entry triggers a write to fifo engine info. There can also be multiple engines with same type, so accumulate interrupts and reset ids from all of them. As the code got fixed, now it reads the engine enum correctly from hardware. We used to compare that against CE0, but we should compare against CE2. gk20a_fifo_reset_engine() uses wrong constants - it is passed a internal numbering of engines, but it compares them against hardware engine enum. Change-Id: Ia59273921c602d2a090f7a5b1404afb0fca2532c Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1147746 Reviewed-by: Konsta Holtta <kholtta@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/fifo_gm20b.c1
-rw-r--r--drivers/gpu/nvgpu/gm20b/hw_top_gm20b.h30
2 files changed, 26 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index e738b1d2..a6d953a4 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -126,4 +126,5 @@ void gm20b_init_fifo(struct gpu_ops *gops)
126 gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature; 126 gops->fifo.get_pbdma_signature = gk20a_fifo_get_pbdma_signature;
127 gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave; 127 gops->fifo.set_runlist_interleave = gk20a_fifo_set_runlist_interleave;
128 gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch; 128 gops->fifo.force_reset_ch = gk20a_fifo_force_reset_ch;
129 gops->fifo.engine_enum_from_type = gk20a_fifo_engine_enum_from_type;
129} 130}
diff --git a/drivers/gpu/nvgpu/gm20b/hw_top_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_top_gm20b.h
index c0ad007d..b0cf6579 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_top_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_top_gm20b.h
@@ -1,5 +1,5 @@
1/* 1/*
2 * Copyright (c) 2014-2015, NVIDIA CORPORATION. All rights reserved. 2 * Copyright (c) 2014-2016, NVIDIA CORPORATION. All rights reserved.
3 * 3 *
4 * This program is free software; you can redistribute it and/or modify it 4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License, 5 * under the terms and conditions of the GNU General Public License,
@@ -138,13 +138,29 @@ static inline u32 top_device_info_type_enum_graphics_f(void)
138{ 138{
139 return 0x0; 139 return 0x0;
140} 140}
141static inline u32 top_device_info_type_enum_copy0_v(void) 141static inline u32 top_device_info_type_enum_copy2_v(void)
142{ 142{
143 return 0x00000001; 143 return 0x00000003;
144}
145static inline u32 top_device_info_type_enum_copy2_f(void)
146{
147 return 0xc;
144} 148}
145static inline u32 top_device_info_type_enum_copy0_f(void) 149static inline u32 top_device_info_engine_v(u32 r)
146{ 150{
147 return 0x4; 151 return (r >> 5) & 0x1;
152}
153static inline u32 top_device_info_runlist_v(u32 r)
154{
155 return (r >> 4) & 0x1;
156}
157static inline u32 top_device_info_intr_v(u32 r)
158{
159 return (r >> 3) & 0x1;
160}
161static inline u32 top_device_info_reset_v(u32 r)
162{
163 return (r >> 2) & 0x1;
148} 164}
149static inline u32 top_device_info_entry_v(u32 r) 165static inline u32 top_device_info_entry_v(u32 r)
150{ 166{
@@ -158,4 +174,8 @@ static inline u32 top_device_info_entry_enum_v(void)
158{ 174{
159 return 0x00000002; 175 return 0x00000002;
160} 176}
177static inline u32 top_device_info_entry_engine_type_v(void)
178{
179 return 0x00000003;
180}
161#endif 181#endif