gpu: nvgpu: Reorg pmu HAL initialization

Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
pmu sub-module of the gpu_ops struct.

Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.

Jira NVGPU-74

Change-Id: I8839ac99e87153637005e23b3013237f57275c54
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530982
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>

5 files changed, 97 insertions, 91 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 4fa1b313..2e904fdf 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -51,11 +51,6 @@ typedef int (*get_ucode_details)(struct gk20a *g, struct flcn_ucode_img *udata);
 static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img);
 static int fecs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img);
 static int gpccs_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img);
-static int gm20b_bootstrap_hs_flcn(struct gk20a *g);
-static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout);
-static int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
-static int gm20b_init_pmu_setup_hw1(struct gk20a *g,
-                void *desc, u32 bl_sz);
 static int lsfm_discover_ucode_images(struct gk20a *g,
         struct ls_flcn_mgr *plsfm);
 static int lsfm_add_ucode_img(struct gk20a *g, struct ls_flcn_mgr *plsfm,
@@ -68,15 +63,6 @@ static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr *plsfm);
 static void lsfm_init_wpr_contents(struct gk20a *g, struct ls_flcn_mgr *plsfm,
         struct nvgpu_mem *nonwpr);
 static void free_acr_resources(struct gk20a *g, struct ls_flcn_mgr *plsfm);
-static int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
-        void *lsfm, u32 *p_bl_gen_desc_size);
-static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
-        void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
-static int gm20b_alloc_blob_space(struct gk20a *g,
-                size_t size, struct nvgpu_mem *mem);
-static bool gm20b_is_priv_load(u32 falcon_id);
-static bool gm20b_is_lazy_bootstrap(u32 falcon_id);
-static void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
 
 /*Globals*/
 static get_ucode_details pmu_acr_supp_ucode_list[] = {
@@ -97,7 +83,7 @@ static void start_gm20b_pmu(struct gk20a *g)
                 pwr_falcon_cpuctl_startcpu_f(1));
 }
 
-static void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf)
+void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf)
 {
         struct mc_carveout_info mem_inf;
 
@@ -108,29 +94,11 @@ static void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf)
         inf->size = mem_inf.size;
 }
 
-static bool gm20b_is_pmu_supported(struct gk20a *g)
+bool gm20b_is_pmu_supported(struct gk20a *g)
 {
         return true;
 }
 
-void gm20b_init_secure_pmu(struct gpu_ops *gops)
-{
-        gops->pmu.is_pmu_supported = gm20b_is_pmu_supported;
-        gops->pmu.prepare_ucode = prepare_ucode_blob;
-        gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn;
-        gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap;
-        gops->pmu.is_priv_load = gm20b_is_priv_load;
-        gops->pmu.get_wpr = gm20b_wpr_info;
-        gops->pmu.alloc_blob_space = gm20b_alloc_blob_space;
-        gops->pmu.pmu_populate_loader_cfg = gm20b_pmu_populate_loader_cfg;
-        gops->pmu.flcn_populate_bl_dmem_desc = gm20b_flcn_populate_bl_dmem_desc;
-        gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt;
-        gops->pmu.falcon_clear_halt_interrupt_status =
-                        clear_halt_interrupt_status;
-        gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1;
-}
-/* TODO - check if any free blob res needed*/
-
 static int pmu_ucode_details(struct gk20a *g, struct flcn_ucode_img *p_img)
 {
         struct nvgpu_firmware *pmu_fw, *pmu_desc, *pmu_sig;
@@ -334,7 +302,7 @@ rel_sig:
         return err;
 }
 
-static bool gm20b_is_lazy_bootstrap(u32 falcon_id)
+bool gm20b_is_lazy_bootstrap(u32 falcon_id)
 {
         bool enable_status = false;
 
@@ -352,7 +320,7 @@ static bool gm20b_is_lazy_bootstrap(u32 falcon_id)
         return enable_status;
 }
 
-static bool gm20b_is_priv_load(u32 falcon_id)
+bool gm20b_is_priv_load(u32 falcon_id)
 {
         bool enable_status = false;
 
@@ -370,7 +338,7 @@ static bool gm20b_is_priv_load(u32 falcon_id)
         return enable_status;
 }
 
-static int gm20b_alloc_blob_space(struct gk20a *g,
+int gm20b_alloc_blob_space(struct gk20a *g,
                 size_t size, struct nvgpu_mem *mem)
 {
         int err;
@@ -554,7 +522,7 @@ static int lsfm_discover_ucode_images(struct gk20a *g,
 }
 
 
-static int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
+int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
         void *lsfm, u32 *p_bl_gen_desc_size)
 {
         struct wpr_carveout_info wpr_inf;
@@ -626,7 +594,7 @@ static int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
         return 0;
 }
 
-static int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
+int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
         void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid)
 {
         struct wpr_carveout_info wpr_inf;
@@ -1066,7 +1034,7 @@ static int lsf_gen_wpr_requirements(struct gk20a *g, struct ls_flcn_mgr *plsfm)
 
 /*Loads ACR bin to FB mem and bootstraps PMU with bootloader code
  * start and end are addresses of ucode blob in non-WPR region*/
-static int gm20b_bootstrap_hs_flcn(struct gk20a *g)
+int gm20b_bootstrap_hs_flcn(struct gk20a *g)
 {
         struct mm_gk20a *mm = &g->mm;
         struct vm_gk20a *vm = mm->pmu.vm;
@@ -1291,7 +1259,7 @@ int gm20b_init_nspmu_setup_hw1(struct gk20a *g)
         return err;
 }
 
-static int gm20b_init_pmu_setup_hw1(struct gk20a *g,
+int gm20b_init_pmu_setup_hw1(struct gk20a *g,
                 void *desc, u32 bl_sz)
 {
 
@@ -1461,7 +1429,7 @@ err_done:
 *       @param[in]      timeout_ms      Timeout in msec for PMU to halt
 *       @return '0' if PMU halts
 */
-static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms)
+int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms)
 {
         struct nvgpu_pmu *pmu = &g->pmu;
         u32 data = 0;
@@ -1490,7 +1458,7 @@ static int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms)
 *       @param[in]      timeout_ms      Timeout in msec for halt to clear
 *       @return '0' if PMU halt irq status is clear
 */
-static int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout_ms)
+int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout_ms)
 {
         struct nvgpu_pmu *pmu = &g->pmu;
         int status = 0;
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
index 84478611..6568d62f 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h
@@ -24,8 +24,21 @@
 #define GM20B_FECS_UCODE_SIG "fecs_sig.bin"
 #define T18x_GPCCS_UCODE_SIG "gpccs_sig.bin"
 
-void gm20b_init_secure_pmu(struct gpu_ops *gops);
+bool gm20b_is_pmu_supported(struct gk20a *g);
 int prepare_ucode_blob(struct gk20a *g);
+int gm20b_bootstrap_hs_flcn(struct gk20a *g);
+bool gm20b_is_lazy_bootstrap(u32 falcon_id);
+bool gm20b_is_priv_load(u32 falcon_id);
+void gm20b_wpr_info(struct gk20a *g, struct wpr_carveout_info *inf);
+int gm20b_alloc_blob_space(struct gk20a *g, size_t size, struct nvgpu_mem *mem);
+int gm20b_pmu_populate_loader_cfg(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size);
+int gm20b_flcn_populate_bl_dmem_desc(struct gk20a *g,
+        void *lsfm, u32 *p_bl_gen_desc_size, u32 falconid);
+int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_ms);
+int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout);
+int gm20b_init_pmu_setup_hw1(struct gk20a *g, void *desc, u32 bl_sz);
+
 int gm20b_pmu_setup_sw(struct gk20a *g);
 int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt);
 int gm20b_init_nspmu_setup_hw1(struct gk20a *g);
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 073c377e..38e8934b 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -26,6 +26,7 @@
 #include "gk20a/flcn_gk20a.h"
 #include "gk20a/priv_ring_gk20a.h"
 #include "gk20a/regops_gk20a.h"
+#include "gk20a/pmu_gk20a.h"
 
 #include "ltc_gm20b.h"
 #include "gr_gm20b.h"
@@ -42,6 +43,7 @@
 #include "therm_gm20b.h"
 #include "bus_gm20b.h"
 #include "hal_gm20b.h"
+#include "acr_gm20b.h"
 
 #include <nvgpu/debug.h>
 #include <nvgpu/bug.h>
@@ -53,6 +55,8 @@
 #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_top_gm20b.h>
+#include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
+#include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
 
 #define PRIV_SECURITY_DISABLE 0x01
 
@@ -313,6 +317,31 @@ static const struct gpu_ops gm20b_ops = {
                 .init_therm_setup_hw = gm20b_init_therm_setup_hw,
                 .elcg_init_idle_filters = gk20a_elcg_init_idle_filters,
         },
+        .pmu = {
+                .pmu_setup_elpg = gm20b_pmu_setup_elpg,
+                .pmu_get_queue_head = pwr_pmu_queue_head_r,
+                .pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v,
+                .pmu_get_queue_tail = pwr_pmu_queue_tail_r,
+                .pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v,
+                .pmu_queue_head = gk20a_pmu_queue_head,
+                .pmu_queue_tail = gk20a_pmu_queue_tail,
+                .pmu_msgq_tail = gk20a_pmu_msgq_tail,
+                .pmu_mutex_size = pwr_pmu_mutex__size_1_v,
+                .pmu_mutex_acquire = gk20a_pmu_mutex_acquire,
+                .pmu_mutex_release = gk20a_pmu_mutex_release,
+                .write_dmatrfbase = gm20b_write_dmatrfbase,
+                .pmu_elpg_statistics = gk20a_pmu_elpg_statistics,
+                .pmu_pg_init_param = NULL,
+                .pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list,
+                .pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list,
+                .pmu_is_lpwr_feature_supported = NULL,
+                .pmu_lpwr_enable_pg = NULL,
+                .pmu_lpwr_disable_pg = NULL,
+                .pmu_pg_param_post_init = NULL,
+                .dump_secure_fuses = pmu_dump_security_fuses_gm20b,
+                .reset_engine = gk20a_pmu_engine_reset,
+                .is_engine_in_reset = gk20a_pmu_is_engine_in_reset,
+        },
         .clk = {
                 .init_clk_support = gm20b_init_clk_support,
                 .suspend_clk_support = gm20b_suspend_clk_support,
@@ -422,6 +451,7 @@ int gm20b_init_hal(struct gk20a *g)
         gops->gr_ctx = gm20b_ops.gr_ctx;
         gops->mm = gm20b_ops.mm;
         gops->therm = gm20b_ops.therm;
+        gops->pmu = gm20b_ops.pmu;
         /*
          * clk must be assigned member by member
          * since some clk ops are assigned during probe prior to HAL init
@@ -483,9 +513,44 @@ int gm20b_init_hal(struct gk20a *g)
                 }
         }
 #endif
+
+        /* priv security dependent ops */
+        if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
+                /* Add in ops from gm20b acr */
+                gops->pmu.is_pmu_supported = gm20b_is_pmu_supported;
+                gops->pmu.prepare_ucode = prepare_ucode_blob;
+                gops->pmu.pmu_setup_hw_and_bootstrap = gm20b_bootstrap_hs_flcn;
+                gops->pmu.is_lazy_bootstrap = gm20b_is_lazy_bootstrap;
+                gops->pmu.is_priv_load = gm20b_is_priv_load;
+                gops->pmu.get_wpr = gm20b_wpr_info;
+                gops->pmu.alloc_blob_space = gm20b_alloc_blob_space;
+                gops->pmu.pmu_populate_loader_cfg =
+                        gm20b_pmu_populate_loader_cfg;
+                gops->pmu.flcn_populate_bl_dmem_desc =
+                        gm20b_flcn_populate_bl_dmem_desc;
+                gops->pmu.falcon_wait_for_halt = pmu_wait_for_halt;
+                gops->pmu.falcon_clear_halt_interrupt_status =
+                        clear_halt_interrupt_status;
+                gops->pmu.init_falcon_setup_hw = gm20b_init_pmu_setup_hw1;
+
+                gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
+                gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
+        } else {
+                /* Inherit from gk20a */
+                gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
+                gops->pmu.prepare_ucode = nvgpu_pmu_prepare_ns_ucode_blob;
+                gops->pmu.pmu_setup_hw_and_bootstrap = gk20a_init_pmu_setup_hw1;
+                gops->pmu.pmu_nsbootstrap = pmu_bootstrap;
+
+                gops->pmu.load_lsfalcon_ucode = NULL;
+                gops->pmu.init_wpr_region = NULL;
+        }
+
+        __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
+        g->pmu_lsf_pmu_wpr_init_done = 0;
         g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
+
         gm20b_init_gr(g);
-        gm20b_init_pmu_ops(g);
 
         gm20b_init_uncompressed_kind_map();
         gm20b_init_kind_attr();
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index a5940fcf..99241a53 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -102,7 +102,7 @@ static struct pg_init_sequence_list _pginitseq_gm20b[] = {
                 { 0x0010e040, 0x00000000},
 };
 
-static int gm20b_pmu_setup_elpg(struct gk20a *g)
+int gm20b_pmu_setup_elpg(struct gk20a *g)
 {
         int ret = 0;
         u32 reg_writes;
@@ -226,7 +226,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags)
         return;
 }
 
-static int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
+int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
 {
         u32  err = 0;
         u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES;
@@ -261,7 +261,7 @@ void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr)
 }
 
 /*Dump Security related fuses*/
-static void pmu_dump_security_fuses_gm20b(struct gk20a *g)
+void pmu_dump_security_fuses_gm20b(struct gk20a *g)
 {
         u32 val;
 
@@ -272,45 +272,3 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g)
         nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val);
         nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val);
 }
-
-void gm20b_init_pmu_ops(struct gk20a *g)
-{
-        struct gpu_ops *gops = &g->ops;
-
-        if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {
-                gm20b_init_secure_pmu(gops);
-                gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
-                gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
-        } else {
-                gk20a_init_pmu_ops(gops);
-                gops->pmu.pmu_setup_hw_and_bootstrap =
-                        gm20b_init_nspmu_setup_hw1;
-                gops->pmu.load_lsfalcon_ucode = NULL;
-                gops->pmu.init_wpr_region = NULL;
-        }
-        gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg;
-        gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r;
-        gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v;
-        gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r;
-        gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v;
-        gops->pmu.pmu_queue_head = gk20a_pmu_queue_head;
-        gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail;
-        gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail;
-        gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v;
-        gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire;
-        gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release;
-        g->pmu_lsf_pmu_wpr_init_done = 0;
-        __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
-        gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase;
-        gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics;
-        gops->pmu.pmu_pg_init_param = NULL;
-        gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list;
-        gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list;
-        gops->pmu.pmu_is_lpwr_feature_supported = NULL;
-        gops->pmu.pmu_lpwr_enable_pg = NULL;
-        gops->pmu.pmu_lpwr_disable_pg = NULL;
-        gops->pmu.pmu_pg_param_post_init = NULL;
-        gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b;
-        gops->pmu.reset_engine = gk20a_pmu_engine_reset;
-        gops->pmu.is_engine_in_reset = gk20a_pmu_is_engine_in_reset;
-}
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
index 424fab35..ed3a8700 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.h
@@ -18,7 +18,9 @@
 
 struct gk20a;
 
-void gm20b_init_pmu_ops(struct gk20a *g);
+int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask);
+int gm20b_pmu_setup_elpg(struct gk20a *g);
+void pmu_dump_security_fuses_gm20b(struct gk20a *g);
 void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags);
 int gm20b_pmu_init_acr(struct gk20a *g);
 void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr);