diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2017-10-13 11:13:45 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-10-17 12:25:23 -0400 |
commit | 5c5b52dce54fa09d16ae38a232a0e17b4729b472 (patch) | |
tree | e1b6821896df1fd741db9baa831838340458c229 /drivers/gpu/nvgpu/gm20b | |
parent | 682abd7b5cd544f83b8905830cd9b738c458be7f (diff) |
gpu: nvgpu: Use internal nvgpu_warpstate
Replace use of ioctl structure warpstate with internal
nvgpu_warptate.
JIRA NVGPU-259
Change-Id: I5170364d0443235cee471b87fa332fc09588f5d3
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1578684
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 2 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 3 |
2 files changed, 3 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 05c6dc5f..92096cfa 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -1140,7 +1140,7 @@ void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem) | |||
1140 | nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_ctl_o(), cde_v); | 1140 | nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_ctl_o(), cde_v); |
1141 | } | 1141 | } |
1142 | 1142 | ||
1143 | void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) | 1143 | void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state) |
1144 | { | 1144 | { |
1145 | /* Check if we have at least one valid warp */ | 1145 | /* Check if we have at least one valid warp */ |
1146 | /* get paused state on maxwell */ | 1146 | /* get paused state on maxwell */ |
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index c7a84b0a..67f1ea29 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -26,6 +26,7 @@ | |||
26 | #define _NVHOST_GM20B_GR_MMU_H | 26 | #define _NVHOST_GM20B_GR_MMU_H |
27 | 27 | ||
28 | struct gk20a; | 28 | struct gk20a; |
29 | struct nvgpu_warpstate; | ||
29 | 30 | ||
30 | enum { | 31 | enum { |
31 | MAXWELL_B = 0xB197, | 32 | MAXWELL_B = 0xB197, |
@@ -112,7 +113,7 @@ u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g); | |||
112 | u32 gr_gm20b_get_max_fbps_count(struct gk20a *g); | 113 | u32 gr_gm20b_get_max_fbps_count(struct gk20a *g); |
113 | void gr_gm20b_init_cyclestats(struct gk20a *g); | 114 | void gr_gm20b_init_cyclestats(struct gk20a *g); |
114 | void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem); | 115 | void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem); |
115 | void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state); | 116 | void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); |
116 | void gr_gm20b_get_access_map(struct gk20a *g, | 117 | void gr_gm20b_get_access_map(struct gk20a *g, |
117 | u32 **whitelist, int *num_entries); | 118 | u32 **whitelist, int *num_entries); |
118 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); | 119 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc); |