diff options
author | Alex Waterman <alexw@nvidia.com> | 2018-02-28 12:19:19 -0500 |
---|---|---|
committer | Srikar Srimath Tirumala <srikars@nvidia.com> | 2018-02-28 16:49:22 -0500 |
commit | 5a35a95654d561fce09a3b9abf6b82bb7a29d74b (patch) | |
tree | 119a07134188d8e06c29a570dd8c6b143f39c9e1 /drivers/gpu/nvgpu/gm20b | |
parent | 3fdd8e38b280123fd13bcc4f3fd8928c15e94db6 (diff) |
Revert "gpu: nvgpu: Get coherency on gv100 + NVLINK working"
Also revert other changes related to IO coherence. This may be the
culprit in a recent dev-kernel lockdown.
Bug 2070609
Change-Id: Ida178aef161fadbc6db9512521ea51c702c1564b
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1665914
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Srikar Srimath Tirumala <srikars@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/bus_gm20b.c | 6 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | 12 |
2 files changed, 7 insertions, 11 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c index cdd70d5b..34c8d4b7 100644 --- a/drivers/gpu/nvgpu/gm20b/bus_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/bus_gm20b.c | |||
@@ -25,7 +25,6 @@ | |||
25 | #include <nvgpu/timers.h> | 25 | #include <nvgpu/timers.h> |
26 | #include <nvgpu/bus.h> | 26 | #include <nvgpu/bus.h> |
27 | #include <nvgpu/mm.h> | 27 | #include <nvgpu/mm.h> |
28 | #include <nvgpu/enabled.h> | ||
29 | 28 | ||
30 | #include "bus_gm20b.h" | 29 | #include "bus_gm20b.h" |
31 | #include "gk20a/gk20a.h" | 30 | #include "gk20a/gk20a.h" |
@@ -44,9 +43,8 @@ int gm20b_bus_bar1_bind(struct gk20a *g, struct nvgpu_mem *bar1_inst) | |||
44 | 43 | ||
45 | gk20a_writel(g, bus_bar1_block_r(), | 44 | gk20a_writel(g, bus_bar1_block_r(), |
46 | nvgpu_aperture_mask(g, bar1_inst, | 45 | nvgpu_aperture_mask(g, bar1_inst, |
47 | bus_bar1_block_target_sys_mem_ncoh_f(), | 46 | bus_bar1_block_target_sys_mem_ncoh_f(), |
48 | bus_bar1_block_target_sys_mem_coh_f(), | 47 | bus_bar1_block_target_vid_mem_f()) | |
49 | bus_bar1_block_target_vid_mem_f()) | | ||
50 | bus_bar1_block_mode_virtual_f() | | 48 | bus_bar1_block_mode_virtual_f() | |
51 | bus_bar1_block_ptr_f(ptr_v)); | 49 | bus_bar1_block_ptr_f(ptr_v)); |
52 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); | 50 | nvgpu_timeout_init(g, &timeout, 1000, NVGPU_TIMER_RETRY_TIMER); |
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c index 15612995..0762e8bd 100644 --- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c | |||
@@ -32,7 +32,6 @@ | |||
32 | #include <nvgpu/atomic.h> | 32 | #include <nvgpu/atomic.h> |
33 | #include <nvgpu/barrier.h> | 33 | #include <nvgpu/barrier.h> |
34 | #include <nvgpu/mm.h> | 34 | #include <nvgpu/mm.h> |
35 | #include <nvgpu/enabled.h> | ||
36 | 35 | ||
37 | #include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h> | 36 | #include <nvgpu/hw/gm20b/hw_ccsr_gm20b.h> |
38 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | 37 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> |
@@ -52,12 +51,11 @@ void channel_gm20b_bind(struct channel_gk20a *c) | |||
52 | 51 | ||
53 | 52 | ||
54 | gk20a_writel(g, ccsr_channel_inst_r(c->chid), | 53 | gk20a_writel(g, ccsr_channel_inst_r(c->chid), |
55 | ccsr_channel_inst_ptr_f(inst_ptr) | | 54 | ccsr_channel_inst_ptr_f(inst_ptr) | |
56 | nvgpu_aperture_mask(g, &c->inst_block, | 55 | nvgpu_aperture_mask(g, &c->inst_block, |
57 | ccsr_channel_inst_target_sys_mem_ncoh_f(), | 56 | ccsr_channel_inst_target_sys_mem_ncoh_f(), |
58 | ccsr_channel_inst_target_sys_mem_coh_f(), | 57 | ccsr_channel_inst_target_vid_mem_f()) | |
59 | ccsr_channel_inst_target_vid_mem_f()) | | 58 | ccsr_channel_inst_bind_true_f()); |
60 | ccsr_channel_inst_bind_true_f()); | ||
61 | 59 | ||
62 | gk20a_writel(g, ccsr_channel_r(c->chid), | 60 | gk20a_writel(g, ccsr_channel_r(c->chid), |
63 | (gk20a_readl(g, ccsr_channel_r(c->chid)) & | 61 | (gk20a_readl(g, ccsr_channel_r(c->chid)) & |