gpu: nvgpu: Implement get_rate/set_rate as GPU op

Move clock APIs from gk20a_platform to gpu_ops. At the same time
allow use of internal get_rate/set_rate for querying both GPCCLK
and PWRCLK on iGPU.

At the same time we can replace calls to clk framework with the
new HAL and drop direct dependency to clk framework.

gp10b ops were replaced as a whole at HAL initialization. That
replaces anything set in platform probe stage, so reduce that to
touch only clock gating regs.

Change-Id: Iaf219b1f000d362dbf397d45832f52d25463b31c
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1300113
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

2 files changed, 2 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index ed144c0f..2d932b67 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -13,7 +13,6 @@
 
 #include <linux/delay.h>        /* for mdelay */
 #include <linux/firmware.h>
-#include <linux/clk.h>
 #include <linux/module.h>
 #include <linux/debugfs.h>
 #include <linux/dma-mapping.h>
@@ -1317,7 +1316,6 @@ static int gm20b_init_pmu_setup_hw1(struct gk20a *g,
 
         struct pmu_gk20a *pmu = &g->pmu;
         int err;
-        struct gk20a_platform *platform = dev_get_drvdata(g->dev);
 
         gk20a_dbg_fn("");
 
@@ -1345,7 +1343,7 @@ static int gm20b_init_pmu_setup_hw1(struct gk20a *g,
 
         /*Copying pmu cmdline args*/
         g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu,
-                                clk_get_rate(platform->clk[1]));
+                                g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK));
         g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1);
         g->ops.pmu_ver.set_pmu_cmdline_args_trace_size(
                 pmu, GK20A_PMU_TRACE_BUFSIZE);
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index d9fb2c53..ad041f67 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -185,7 +185,7 @@ int gm20b_init_hal(struct gk20a *g)
         struct gk20a_platform *platform = dev_get_drvdata(g->dev);
         u32 val;
 
-        *gops = gm20b_ops;
+        gops->clock_gating = gm20b_ops.clock_gating;
         gops->securegpccs = false;
         gops->pmupstate = false;
 #ifdef CONFIG_TEGRA_ACR