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authorSunny He <suhe@nvidia.com>2017-08-17 19:11:34 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-24 12:34:43 -0400
commit4b5b67d6d83430d8d670660b1dfc9cf024d60d88 (patch)
tree541a421438fe849ee4b1ab9e6bdfa9e8b6ee4485 /drivers/gpu/nvgpu/gm20b
parent82ba1277f3da7379ed6b8288c04bb91db008549c (diff)
gpu: nvgpu: Reorg gr HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ie37638f442fd68aca8a7ade5f297118447bdc91e Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542989 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.c222
-rw-r--r--drivers/gpu/nvgpu/gm20b/gr_gm20b.h87
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c120
3 files changed, 255 insertions, 174 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 5fcc3f7b..30991102 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -36,7 +36,7 @@
36#include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h> 36#include <nvgpu/hw/gm20b/hw_ctxsw_prog_gm20b.h>
37#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> 37#include <nvgpu/hw/gm20b/hw_fuse_gm20b.h>
38 38
39static void gr_gm20b_init_gpc_mmu(struct gk20a *g) 39void gr_gm20b_init_gpc_mmu(struct gk20a *g)
40{ 40{
41 u32 temp; 41 u32 temp;
42 42
@@ -73,7 +73,7 @@ static void gr_gm20b_init_gpc_mmu(struct gk20a *g)
73 gk20a_readl(g, fb_fbhub_num_active_ltcs_r())); 73 gk20a_readl(g, fb_fbhub_num_active_ltcs_r()));
74} 74}
75 75
76static void gr_gm20b_bundle_cb_defaults(struct gk20a *g) 76void gr_gm20b_bundle_cb_defaults(struct gk20a *g)
77{ 77{
78 struct gr_gk20a *gr = &g->gr; 78 struct gr_gk20a *gr = &g->gr;
79 79
@@ -85,7 +85,7 @@ static void gr_gm20b_bundle_cb_defaults(struct gk20a *g)
85 gr_pd_ab_dist_cfg2_token_limit_init_v(); 85 gr_pd_ab_dist_cfg2_token_limit_init_v();
86} 86}
87 87
88static void gr_gm20b_cb_size_default(struct gk20a *g) 88void gr_gm20b_cb_size_default(struct gk20a *g)
89{ 89{
90 struct gr_gk20a *gr = &g->gr; 90 struct gr_gk20a *gr = &g->gr;
91 91
@@ -96,7 +96,7 @@ static void gr_gm20b_cb_size_default(struct gk20a *g)
96 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v(); 96 gr_gpc0_ppc0_cbm_alpha_cb_size_v_default_v();
97} 97}
98 98
99static int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g) 99int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g)
100{ 100{
101 struct gr_gk20a *gr = &g->gr; 101 struct gr_gk20a *gr = &g->gr;
102 int size; 102 int size;
@@ -134,7 +134,7 @@ void gr_gm20b_commit_global_attrib_cb(struct gk20a *g,
134 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch); 134 gr_gpcs_tpcs_mpc_vtg_cb_global_base_addr_valid_true_f(), patch);
135} 135}
136 136
137static void gr_gm20b_commit_global_bundle_cb(struct gk20a *g, 137void gr_gm20b_commit_global_bundle_cb(struct gk20a *g,
138 struct channel_ctx_gk20a *ch_ctx, 138 struct channel_ctx_gk20a *ch_ctx,
139 u64 addr, u64 size, bool patch) 139 u64 addr, u64 size, bool patch)
140{ 140{
@@ -170,7 +170,7 @@ static void gr_gm20b_commit_global_bundle_cb(struct gk20a *g,
170 170
171} 171}
172 172
173static int gr_gm20b_commit_global_cb_manager(struct gk20a *g, 173int gr_gm20b_commit_global_cb_manager(struct gk20a *g,
174 struct channel_gk20a *c, bool patch) 174 struct channel_gk20a *c, bool patch)
175{ 175{
176 struct gr_gk20a *gr = &g->gr; 176 struct gr_gk20a *gr = &g->gr;
@@ -250,7 +250,7 @@ static int gr_gm20b_commit_global_cb_manager(struct gk20a *g,
250 return 0; 250 return 0;
251} 251}
252 252
253static void gr_gm20b_commit_global_pagepool(struct gk20a *g, 253void gr_gm20b_commit_global_pagepool(struct gk20a *g,
254 struct channel_ctx_gk20a *ch_ctx, 254 struct channel_ctx_gk20a *ch_ctx,
255 u64 addr, u32 size, bool patch) 255 u64 addr, u32 size, bool patch)
256{ 256{
@@ -276,7 +276,7 @@ void gr_gm20b_set_rd_coalesce(struct gk20a *g, u32 data)
276 gk20a_dbg_fn("done"); 276 gk20a_dbg_fn("done");
277} 277}
278 278
279static int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr, 279int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr,
280 u32 class_num, u32 offset, u32 data) 280 u32 class_num, u32 offset, u32 data)
281{ 281{
282 gk20a_dbg_fn(""); 282 gk20a_dbg_fn("");
@@ -318,7 +318,7 @@ fail:
318 return -EINVAL; 318 return -EINVAL;
319} 319}
320 320
321static void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data) 321void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
322{ 322{
323 struct gr_gk20a *gr = &g->gr; 323 struct gr_gk20a *gr = &g->gr;
324 u32 gpc_index, ppc_index, stride, val; 324 u32 gpc_index, ppc_index, stride, val;
@@ -368,7 +368,7 @@ static void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data)
368 } 368 }
369} 369}
370 370
371static void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data) 371void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data)
372{ 372{
373 struct gr_gk20a *gr = &g->gr; 373 struct gr_gk20a *gr = &g->gr;
374 u32 gpc_index, ppc_index, stride, val; 374 u32 gpc_index, ppc_index, stride, val;
@@ -423,7 +423,7 @@ static void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data)
423 } 423 }
424} 424}
425 425
426static void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g) 426void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g)
427{ 427{
428 /* setup sm warp esr report masks */ 428 /* setup sm warp esr report masks */
429 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(), 429 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r(),
@@ -456,7 +456,7 @@ static void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g)
456 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f()); 456 gr_gpcs_tpcs_sm_hww_global_esr_report_mask_multiple_warp_errors_report_f());
457} 457}
458 458
459static bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num) 459bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num)
460{ 460{
461 bool valid = false; 461 bool valid = false;
462 462
@@ -476,7 +476,7 @@ static bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num)
476 return valid; 476 return valid;
477} 477}
478 478
479static bool gr_gm20b_is_valid_gfx_class(struct gk20a *g, u32 class_num) 479bool gr_gm20b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
480{ 480{
481 if (class_num == MAXWELL_B) 481 if (class_num == MAXWELL_B)
482 return true; 482 return true;
@@ -484,7 +484,7 @@ static bool gr_gm20b_is_valid_gfx_class(struct gk20a *g, u32 class_num)
484 return false; 484 return false;
485} 485}
486 486
487static bool gr_gm20b_is_valid_compute_class(struct gk20a *g, u32 class_num) 487bool gr_gm20b_is_valid_compute_class(struct gk20a *g, u32 class_num)
488{ 488{
489 if (class_num == MAXWELL_COMPUTE_B) 489 if (class_num == MAXWELL_COMPUTE_B)
490 return true; 490 return true;
@@ -502,7 +502,7 @@ static const u32 _num_sm_dsm_perf_ctrl_regs = 2;
502static u32 *_sm_dsm_perf_regs; 502static u32 *_sm_dsm_perf_regs;
503static u32 _sm_dsm_perf_ctrl_regs[2]; 503static u32 _sm_dsm_perf_ctrl_regs[2];
504 504
505static void gr_gm20b_init_sm_dsm_reg_info(void) 505void gr_gm20b_init_sm_dsm_reg_info(void)
506{ 506{
507 if (_sm_dsm_perf_ctrl_regs[0] != 0) 507 if (_sm_dsm_perf_ctrl_regs[0] != 0)
508 return; 508 return;
@@ -513,7 +513,7 @@ static void gr_gm20b_init_sm_dsm_reg_info(void)
513 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r(); 513 gr_pri_gpc0_tpc0_sm_dsm_perf_counter_control5_r();
514} 514}
515 515
516static void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g, 516void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g,
517 u32 *num_sm_dsm_perf_regs, 517 u32 *num_sm_dsm_perf_regs,
518 u32 **sm_dsm_perf_regs, 518 u32 **sm_dsm_perf_regs,
519 u32 *perf_register_stride) 519 u32 *perf_register_stride)
@@ -523,7 +523,7 @@ static void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g,
523 *perf_register_stride = 0; 523 *perf_register_stride = 0;
524} 524}
525 525
526static void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g, 526void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
527 u32 *num_sm_dsm_perf_ctrl_regs, 527 u32 *num_sm_dsm_perf_ctrl_regs,
528 u32 **sm_dsm_perf_ctrl_regs, 528 u32 **sm_dsm_perf_ctrl_regs,
529 u32 *ctrl_register_stride) 529 u32 *ctrl_register_stride)
@@ -535,7 +535,7 @@ static void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
535 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v(); 535 ctxsw_prog_extended_sm_dsm_perf_counter_control_register_stride_v();
536} 536}
537 537
538static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) 538u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
539{ 539{
540 u32 val; 540 u32 val;
541 struct gr_gk20a *gr = &g->gr; 541 struct gr_gk20a *gr = &g->gr;
@@ -546,7 +546,7 @@ static u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
546 return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1); 546 return (~val) & ((0x1 << gr->max_tpc_per_gpc_count) - 1);
547} 547}
548 548
549static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index) 549void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
550{ 550{
551 nvgpu_tegra_fuse_write_bypass(g, 0x1); 551 nvgpu_tegra_fuse_write_bypass(g, 0x1);
552 nvgpu_tegra_fuse_write_access_sw(g, 0x0); 552 nvgpu_tegra_fuse_write_access_sw(g, 0x0);
@@ -563,7 +563,7 @@ static void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index)
563 } 563 }
564} 564}
565 565
566static void gr_gm20b_load_tpc_mask(struct gk20a *g) 566void gr_gm20b_load_tpc_mask(struct gk20a *g)
567{ 567{
568 u32 pes_tpc_mask = 0, fuse_tpc_mask; 568 u32 pes_tpc_mask = 0, fuse_tpc_mask;
569 u32 gpc, pes; 569 u32 gpc, pes;
@@ -588,7 +588,7 @@ static void gr_gm20b_load_tpc_mask(struct gk20a *g)
588 } 588 }
589} 589}
590 590
591static void gr_gm20b_program_sm_id_numbering(struct gk20a *g, 591void gr_gm20b_program_sm_id_numbering(struct gk20a *g,
592 u32 gpc, u32 tpc, u32 smid) 592 u32 gpc, u32 tpc, u32 smid)
593{ 593{
594 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE); 594 u32 gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_GPC_STRIDE);
@@ -604,7 +604,7 @@ static void gr_gm20b_program_sm_id_numbering(struct gk20a *g,
604 gr_gpc0_tpc0_pe_cfg_smid_value_f(smid)); 604 gr_gpc0_tpc0_pe_cfg_smid_value_f(smid));
605} 605}
606 606
607static int gr_gm20b_load_smid_config(struct gk20a *g) 607int gr_gm20b_load_smid_config(struct gk20a *g)
608{ 608{
609 u32 *tpc_sm_id; 609 u32 *tpc_sm_id;
610 u32 i, j; 610 u32 i, j;
@@ -669,7 +669,7 @@ int gr_gm20b_init_fs_state(struct gk20a *g)
669 return 0; 669 return 0;
670} 670}
671 671
672static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base, 672int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base,
673 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset) 673 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset)
674{ 674{
675 gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(), 675 gk20a_writel(g, reg_offset + gr_fecs_dmactl_r(),
@@ -697,7 +697,7 @@ static bool gr_gm20b_is_tpc_addr_shared(struct gk20a *g, u32 addr)
697 tpc_in_gpc_stride)); 697 tpc_in_gpc_stride));
698} 698}
699 699
700static bool gr_gm20b_is_tpc_addr(struct gk20a *g, u32 addr) 700bool gr_gm20b_is_tpc_addr(struct gk20a *g, u32 addr)
701{ 701{
702 u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_BASE); 702 u32 tpc_in_gpc_base = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_BASE);
703 u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE); 703 u32 tpc_in_gpc_stride = nvgpu_get_litter_value(g, GPU_LIT_TPC_IN_GPC_STRIDE);
@@ -708,7 +708,7 @@ static bool gr_gm20b_is_tpc_addr(struct gk20a *g, u32 addr)
708 || gr_gm20b_is_tpc_addr_shared(g, addr); 708 || gr_gm20b_is_tpc_addr_shared(g, addr);
709} 709}
710 710
711static u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr) 711u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr)
712{ 712{
713 u32 i, start; 713 u32 i, start;
714 u32 num_tpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_TPC_PER_GPC); 714 u32 num_tpcs = nvgpu_get_litter_value(g, GPU_LIT_NUM_TPC_PER_GPC);
@@ -738,7 +738,7 @@ static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g)
738 gr_fecs_falcon_hwcfg_r()); 738 gr_fecs_falcon_hwcfg_r());
739} 739}
740 740
741static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) 741int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
742{ 742{
743 u32 err, flags; 743 u32 err, flags;
744 u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() - 744 u32 reg_offset = gr_gpcs_gpccs_falcon_hwcfg_r() -
@@ -819,14 +819,14 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
819} 819}
820#else 820#else
821 821
822static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) 822int gr_gm20b_load_ctxsw_ucode(struct gk20a *g)
823{ 823{
824 return -EPERM; 824 return -EPERM;
825} 825}
826 826
827#endif 827#endif
828 828
829static void gr_gm20b_detect_sm_arch(struct gk20a *g) 829void gr_gm20b_detect_sm_arch(struct gk20a *g)
830{ 830{
831 u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r()); 831 u32 v = gk20a_readl(g, gr_gpc0_tpc0_sm_arch_r());
832 832
@@ -838,12 +838,12 @@ static void gr_gm20b_detect_sm_arch(struct gk20a *g)
838 gr_gpc0_tpc0_sm_arch_warp_count_v(v); 838 gr_gpc0_tpc0_sm_arch_warp_count_v(v);
839} 839}
840 840
841static u32 gr_gm20b_pagepool_default_size(struct gk20a *g) 841u32 gr_gm20b_pagepool_default_size(struct gk20a *g)
842{ 842{
843 return gr_scc_pagepool_total_pages_hwmax_value_v(); 843 return gr_scc_pagepool_total_pages_hwmax_value_v();
844} 844}
845 845
846static int gr_gm20b_alloc_gr_ctx(struct gk20a *g, 846int gr_gm20b_alloc_gr_ctx(struct gk20a *g,
847 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm, 847 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
848 u32 class, 848 u32 class,
849 u32 flags) 849 u32 flags)
@@ -864,7 +864,7 @@ static int gr_gm20b_alloc_gr_ctx(struct gk20a *g,
864 return 0; 864 return 0;
865} 865}
866 866
867static void gr_gm20b_update_ctxsw_preemption_mode(struct gk20a *g, 867void gr_gm20b_update_ctxsw_preemption_mode(struct gk20a *g,
868 struct channel_ctx_gk20a *ch_ctx, 868 struct channel_ctx_gk20a *ch_ctx,
869 struct nvgpu_mem *mem) 869 struct nvgpu_mem *mem)
870{ 870{
@@ -884,7 +884,7 @@ static void gr_gm20b_update_ctxsw_preemption_mode(struct gk20a *g,
884 gk20a_dbg_fn("done"); 884 gk20a_dbg_fn("done");
885} 885}
886 886
887static int gr_gm20b_dump_gr_status_regs(struct gk20a *g, 887int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
888 struct gk20a_debug_output *o) 888 struct gk20a_debug_output *o)
889{ 889{
890 struct gr_gk20a *gr = &g->gr; 890 struct gr_gk20a *gr = &g->gr;
@@ -1022,7 +1022,7 @@ static int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
1022 return 0; 1022 return 0;
1023} 1023}
1024 1024
1025static int gr_gm20b_update_pc_sampling(struct channel_gk20a *c, 1025int gr_gm20b_update_pc_sampling(struct channel_gk20a *c,
1026 bool enable) 1026 bool enable)
1027{ 1027{
1028 struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx; 1028 struct channel_ctx_gk20a *ch_ctx = &c->ch_ctx;
@@ -1051,7 +1051,7 @@ static int gr_gm20b_update_pc_sampling(struct channel_gk20a *c,
1051 return 0; 1051 return 0;
1052} 1052}
1053 1053
1054static u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g) 1054u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g)
1055{ 1055{
1056 u32 fbp_en_mask, opt_fbio; 1056 u32 fbp_en_mask, opt_fbio;
1057 u32 tmp, max_fbps_count; 1057 u32 tmp, max_fbps_count;
@@ -1066,7 +1066,7 @@ static u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g)
1066 return fbp_en_mask; 1066 return fbp_en_mask;
1067} 1067}
1068 1068
1069static u32 gr_gm20b_get_max_ltc_per_fbp(struct gk20a *g) 1069u32 gr_gm20b_get_max_ltc_per_fbp(struct gk20a *g)
1070{ 1070{
1071 u32 ltc_per_fbp, reg; 1071 u32 ltc_per_fbp, reg;
1072 reg = gk20a_readl(g, top_ltc_per_fbp_r()); 1072 reg = gk20a_readl(g, top_ltc_per_fbp_r());
@@ -1074,7 +1074,7 @@ static u32 gr_gm20b_get_max_ltc_per_fbp(struct gk20a *g)
1074 return ltc_per_fbp; 1074 return ltc_per_fbp;
1075} 1075}
1076 1076
1077static u32 gr_gm20b_get_max_lts_per_ltc(struct gk20a *g) 1077u32 gr_gm20b_get_max_lts_per_ltc(struct gk20a *g)
1078{ 1078{
1079 u32 lts_per_ltc, reg; 1079 u32 lts_per_ltc, reg;
1080 reg = gk20a_readl(g, top_slices_per_ltc_r()); 1080 reg = gk20a_readl(g, top_slices_per_ltc_r());
@@ -1082,7 +1082,7 @@ static u32 gr_gm20b_get_max_lts_per_ltc(struct gk20a *g)
1082 return lts_per_ltc; 1082 return lts_per_ltc;
1083} 1083}
1084 1084
1085static u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g) 1085u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g)
1086{ 1086{
1087 struct gr_gk20a *gr = &g->gr; 1087 struct gr_gk20a *gr = &g->gr;
1088 u32 i, tmp, max_fbps_count, max_ltc_per_fbp; 1088 u32 i, tmp, max_fbps_count, max_ltc_per_fbp;
@@ -1102,7 +1102,7 @@ static u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g)
1102 return gr->fbp_rop_l2_en_mask; 1102 return gr->fbp_rop_l2_en_mask;
1103} 1103}
1104 1104
1105static u32 gr_gm20b_get_max_fbps_count(struct gk20a *g) 1105u32 gr_gm20b_get_max_fbps_count(struct gk20a *g)
1106{ 1106{
1107 u32 tmp, max_fbps_count; 1107 u32 tmp, max_fbps_count;
1108 tmp = gk20a_readl(g, top_num_fbps_r()); 1108 tmp = gk20a_readl(g, top_num_fbps_r());
@@ -1110,7 +1110,7 @@ static u32 gr_gm20b_get_max_fbps_count(struct gk20a *g)
1110 return max_fbps_count; 1110 return max_fbps_count;
1111} 1111}
1112 1112
1113static void gr_gm20b_init_cyclestats(struct gk20a *g) 1113void gr_gm20b_init_cyclestats(struct gk20a *g)
1114{ 1114{
1115#if defined(CONFIG_GK20A_CYCLE_STATS) 1115#if defined(CONFIG_GK20A_CYCLE_STATS)
1116 g->gpu_characteristics.flags |= 1116 g->gpu_characteristics.flags |=
@@ -1122,7 +1122,7 @@ static void gr_gm20b_init_cyclestats(struct gk20a *g)
1122#endif 1122#endif
1123} 1123}
1124 1124
1125static void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem) 1125void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem)
1126{ 1126{
1127 u32 cde_v; 1127 u32 cde_v;
1128 1128
@@ -1131,7 +1131,7 @@ static void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem)
1131 nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_ctl_o(), cde_v); 1131 nvgpu_mem_wr(g, mem, ctxsw_prog_main_image_ctl_o(), cde_v);
1132} 1132}
1133 1133
1134static void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state) 1134void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state)
1135{ 1135{
1136 /* Check if we have at least one valid warp */ 1136 /* Check if we have at least one valid warp */
1137 /* get paused state on maxwell */ 1137 /* get paused state on maxwell */
@@ -1210,7 +1210,7 @@ static void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state)
1210 } 1210 }
1211} 1211}
1212 1212
1213static void gr_gm20b_get_access_map(struct gk20a *g, 1213void gr_gm20b_get_access_map(struct gk20a *g,
1214 u32 **whitelist, int *num_entries) 1214 u32 **whitelist, int *num_entries)
1215{ 1215{
1216 static u32 wl_addr_gm20b[] = { 1216 static u32 wl_addr_gm20b[] = {
@@ -1251,7 +1251,7 @@ static void gr_gm20b_get_access_map(struct gk20a *g,
1251 *num_entries = ARRAY_SIZE(wl_addr_gm20b); 1251 *num_entries = ARRAY_SIZE(wl_addr_gm20b);
1252} 1252}
1253 1253
1254static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) 1254int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
1255{ 1255{
1256 int sm_id; 1256 int sm_id;
1257 struct gr_gk20a *gr = &g->gr; 1257 struct gr_gk20a *gr = &g->gr;
@@ -1281,7 +1281,7 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
1281 return 0; 1281 return 0;
1282} 1282}
1283 1283
1284static int gm20b_gr_update_sm_error_state(struct gk20a *g, 1284int gm20b_gr_update_sm_error_state(struct gk20a *g,
1285 struct channel_gk20a *ch, u32 sm_id, 1285 struct channel_gk20a *ch, u32 sm_id,
1286 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state) 1286 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state)
1287{ 1287{
@@ -1353,7 +1353,7 @@ fail:
1353 return err; 1353 return err;
1354} 1354}
1355 1355
1356static int gm20b_gr_clear_sm_error_state(struct gk20a *g, 1356int gm20b_gr_clear_sm_error_state(struct gk20a *g,
1357 struct channel_gk20a *ch, u32 sm_id) 1357 struct channel_gk20a *ch, u32 sm_id)
1358{ 1358{
1359 u32 gpc, tpc, offset; 1359 u32 gpc, tpc, offset;
@@ -1394,7 +1394,7 @@ fail:
1394 return err; 1394 return err;
1395} 1395}
1396 1396
1397static int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, 1397int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
1398 struct nvgpu_preemption_modes_rec *preemption_modes_rec) 1398 struct nvgpu_preemption_modes_rec *preemption_modes_rec)
1399{ 1399{
1400 preemption_modes_rec->graphics_preemption_mode_flags = 1400 preemption_modes_rec->graphics_preemption_mode_flags =
@@ -1421,7 +1421,7 @@ int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask)
1421 return 0; 1421 return 0;
1422} 1422}
1423 1423
1424static int gm20b_gr_fuse_override(struct gk20a *g) 1424int gm20b_gr_fuse_override(struct gk20a *g)
1425{ 1425{
1426 struct device_node *np = dev_from_gk20a(g)->of_node; 1426 struct device_node *np = dev_from_gk20a(g)->of_node;
1427 u32 *fuses; 1427 u32 *fuses;
@@ -1457,7 +1457,7 @@ static int gm20b_gr_fuse_override(struct gk20a *g)
1457 return 0; 1457 return 0;
1458} 1458}
1459 1459
1460static bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr) 1460bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
1461{ 1461{
1462 u32 ltc_shared_base = ltc_ltcs_ltss_v(); 1462 u32 ltc_shared_base = ltc_ltcs_ltss_v();
1463 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); 1463 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
@@ -1466,7 +1466,7 @@ static bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr)
1466 (addr < (ltc_shared_base + lts_stride)); 1466 (addr < (ltc_shared_base + lts_stride));
1467} 1467}
1468 1468
1469static bool gr_gm20b_is_ltcn_ltss_addr(struct gk20a *g, u32 addr) 1469bool gr_gm20b_is_ltcn_ltss_addr(struct gk20a *g, u32 addr)
1470{ 1470{
1471 u32 lts_shared_base = ltc_ltc0_ltss_v(); 1471 u32 lts_shared_base = ltc_ltc0_ltss_v();
1472 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE); 1472 u32 lts_stride = nvgpu_get_litter_value(g, GPU_LIT_LTS_STRIDE);
@@ -1498,7 +1498,7 @@ static void gr_gm20b_update_ltc_lts_addr(struct gk20a *g, u32 addr, u32 ltc_num,
1498 *priv_addr_table_index = index; 1498 *priv_addr_table_index = index;
1499} 1499}
1500 1500
1501static void gr_gm20b_split_lts_broadcast_addr(struct gk20a *g, u32 addr, 1501void gr_gm20b_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
1502 u32 *priv_addr_table, 1502 u32 *priv_addr_table,
1503 u32 *priv_addr_table_index) 1503 u32 *priv_addr_table_index)
1504{ 1504{
@@ -1518,7 +1518,7 @@ static void gr_gm20b_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
1518 priv_addr_table_index); 1518 priv_addr_table_index);
1519} 1519}
1520 1520
1521static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr, 1521void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
1522 u32 *priv_addr_table, 1522 u32 *priv_addr_table,
1523 u32 *priv_addr_table_index) 1523 u32 *priv_addr_table_index)
1524{ 1524{
@@ -1530,7 +1530,7 @@ static void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
1530 priv_addr_table, priv_addr_table_index); 1530 priv_addr_table, priv_addr_table_index);
1531} 1531}
1532 1532
1533static void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, 1533void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
1534 u32 global_esr) 1534 u32 global_esr)
1535{ 1535{
1536 u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc); 1536 u32 offset = gk20a_gr_gpc_offset(g, gpc) + gk20a_gr_tpc_offset(g, tpc);
@@ -1559,121 +1559,3 @@ void gm20a_gr_disable_rd_coalesce(struct gk20a *g)
1559 1559
1560 gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg); 1560 gk20a_writel(g, gr_gpcs_tpcs_tex_m_dbg2_r(), dbg2_reg);
1561} 1561}
1562
1563void gm20b_init_gr(struct gk20a *g)
1564{
1565 struct gpu_ops *gops = &g->ops;
1566
1567 gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu;
1568 gops->gr.bundle_cb_defaults = gr_gm20b_bundle_cb_defaults;
1569 gops->gr.cb_size_default = gr_gm20b_cb_size_default;
1570 gops->gr.calc_global_ctx_buffer_size =
1571 gr_gm20b_calc_global_ctx_buffer_size;
1572 gops->gr.commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb;
1573 gops->gr.commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb;
1574 gops->gr.commit_global_cb_manager = gr_gm20b_commit_global_cb_manager;
1575 gops->gr.commit_global_pagepool = gr_gm20b_commit_global_pagepool;
1576 gops->gr.handle_sw_method = gr_gm20b_handle_sw_method;
1577 gops->gr.set_alpha_circular_buffer_size = gr_gm20b_set_alpha_circular_buffer_size;
1578 gops->gr.set_circular_buffer_size = gr_gm20b_set_circular_buffer_size;
1579 gops->gr.enable_hww_exceptions = gr_gk20a_enable_hww_exceptions;
1580 gops->gr.is_valid_class = gr_gm20b_is_valid_class;
1581 gops->gr.is_valid_gfx_class = gr_gm20b_is_valid_gfx_class;
1582 gops->gr.is_valid_compute_class = gr_gm20b_is_valid_compute_class;
1583 gops->gr.get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs;
1584 gops->gr.get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs;
1585 gops->gr.init_fs_state = gr_gm20b_init_fs_state;
1586 gops->gr.set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask;
1587 gops->gr.falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments;
1588 if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY))
1589 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
1590 else
1591 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
1592 gops->gr.set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask;
1593 gops->gr.get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask;
1594 gops->gr.free_channel_ctx = gk20a_free_channel_ctx;
1595 gops->gr.alloc_obj_ctx = gk20a_alloc_obj_ctx;
1596 gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull;
1597 gops->gr.get_zcull_info = gr_gk20a_get_zcull_info;
1598 gops->gr.is_tpc_addr = gr_gm20b_is_tpc_addr;
1599 gops->gr.get_tpc_num = gr_gm20b_get_tpc_num;
1600 gops->gr.detect_sm_arch = gr_gm20b_detect_sm_arch;
1601 gops->gr.add_zbc_color = gr_gk20a_add_zbc_color;
1602 gops->gr.add_zbc_depth = gr_gk20a_add_zbc_depth;
1603 gops->gr.zbc_set_table = gk20a_gr_zbc_set_table;
1604 gops->gr.zbc_query_table = gr_gk20a_query_zbc;
1605 gops->gr.pmu_save_zbc = gk20a_pmu_save_zbc;
1606 gops->gr.add_zbc = gr_gk20a_add_zbc;
1607 gops->gr.pagepool_default_size = gr_gm20b_pagepool_default_size;
1608 gops->gr.init_ctx_state = gr_gk20a_init_ctx_state;
1609 gops->gr.alloc_gr_ctx = gr_gm20b_alloc_gr_ctx;
1610 gops->gr.free_gr_ctx = gr_gk20a_free_gr_ctx;
1611 gops->gr.update_ctxsw_preemption_mode =
1612 gr_gm20b_update_ctxsw_preemption_mode;
1613 gops->gr.dump_gr_regs = gr_gm20b_dump_gr_status_regs;
1614 gops->gr.update_pc_sampling = gr_gm20b_update_pc_sampling;
1615 gops->gr.get_fbp_en_mask = gr_gm20b_get_fbp_en_mask;
1616 gops->gr.get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp;
1617 gops->gr.get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc;
1618 gops->gr.get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask;
1619 gops->gr.get_max_fbps_count = gr_gm20b_get_max_fbps_count;
1620 gops->gr.init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info;
1621 gops->gr.wait_empty = gr_gk20a_wait_idle;
1622 gops->gr.init_cyclestats = gr_gm20b_init_cyclestats;
1623 gops->gr.set_sm_debug_mode = gr_gk20a_set_sm_debug_mode;
1624 gops->gr.enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs;
1625 gops->gr.bpt_reg_info = gr_gm20b_bpt_reg_info;
1626 gops->gr.get_access_map = gr_gm20b_get_access_map;
1627 gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error;
1628 gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception;
1629 gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception;
1630 gops->gr.enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions;
1631 gops->gr.enable_exceptions = gk20a_gr_enable_exceptions;
1632 gops->gr.get_lrf_tex_ltc_dram_override = NULL;
1633 gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode;
1634 gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode;
1635 gops->gr.record_sm_error_state = gm20b_gr_record_sm_error_state;
1636 gops->gr.update_sm_error_state = gm20b_gr_update_sm_error_state;
1637 gops->gr.clear_sm_error_state = gm20b_gr_clear_sm_error_state;
1638 gops->gr.suspend_contexts = gr_gk20a_suspend_contexts;
1639 gops->gr.resume_contexts = gr_gk20a_resume_contexts;
1640 gops->gr.get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags;
1641 gops->gr.fuse_override = gm20b_gr_fuse_override;
1642 gops->gr.init_sm_id_table = gr_gk20a_init_sm_id_table;
1643 gops->gr.load_smid_config = gr_gm20b_load_smid_config;
1644 gops->gr.program_sm_id_numbering = gr_gm20b_program_sm_id_numbering;
1645 gops->gr.is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr;
1646 gops->gr.is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr;
1647 gops->gr.split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr;
1648 gops->gr.split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr;
1649 gops->gr.setup_rop_mapping = gr_gk20a_setup_rop_mapping;
1650 gops->gr.program_zcull_mapping = gr_gk20a_program_zcull_mapping;
1651 gops->gr.commit_global_timeslice = gr_gk20a_commit_global_timeslice;
1652 gops->gr.commit_inst = gr_gk20a_commit_inst;
1653 gops->gr.write_zcull_ptr = gr_gk20a_write_zcull_ptr;
1654 gops->gr.write_pm_ptr = gr_gk20a_write_pm_ptr;
1655 gops->gr.init_elcg_mode = gr_gk20a_init_elcg_mode;
1656 gops->gr.load_tpc_mask = gr_gm20b_load_tpc_mask;
1657 gops->gr.inval_icache = gr_gk20a_inval_icache;
1658 gops->gr.trigger_suspend = gr_gk20a_trigger_suspend;
1659 gops->gr.wait_for_pause = gr_gk20a_wait_for_pause;
1660 gops->gr.resume_from_pause = gr_gk20a_resume_from_pause;
1661 gops->gr.clear_sm_errors = gr_gk20a_clear_sm_errors;
1662 gops->gr.tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions;
1663 gops->gr.get_esr_sm_sel = gk20a_gr_get_esr_sm_sel;
1664 gops->gr.sm_debugger_attached = gk20a_gr_sm_debugger_attached;
1665 gops->gr.suspend_single_sm = gk20a_gr_suspend_single_sm;
1666 gops->gr.suspend_all_sms = gk20a_gr_suspend_all_sms;
1667 gops->gr.resume_single_sm = gk20a_gr_resume_single_sm;
1668 gops->gr.resume_all_sms = gk20a_gr_resume_all_sms;
1669 gops->gr.get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr;
1670 gops->gr.get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr;
1671 gops->gr.get_sm_no_lock_down_hww_global_esr_mask =
1672 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask;
1673 gops->gr.lock_down_sm = gk20a_gr_lock_down_sm;
1674 gops->gr.wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down;
1675 gops->gr.clear_sm_hww = gm20b_gr_clear_sm_hww;
1676 gops->gr.init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf;
1677 gops->gr.get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs;
1678 gops->gr.disable_rd_coalesce = gm20a_gr_disable_rd_coalesce;
1679}
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 116a92f4..f81aa728 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -34,12 +34,95 @@ enum {
34#define NVB1C0_SET_RD_COALESCE 0x0228 34#define NVB1C0_SET_RD_COALESCE 0x0228
35 35
36#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0 36#define NVA297_SET_SHADER_EXCEPTIONS_ENABLE_FALSE 0
37void gm20b_init_gr(struct gk20a *g); 37
38void gr_gm20b_commit_global_attrib_cb(struct gk20a *g, 38void gr_gm20b_commit_global_attrib_cb(struct gk20a *g,
39 struct channel_ctx_gk20a *ch_ctx, 39 struct channel_ctx_gk20a *ch_ctx,
40 u64 addr, bool patch); 40 u64 addr, bool patch);
41int gr_gm20b_init_fs_state(struct gk20a *g); 41int gr_gm20b_init_fs_state(struct gk20a *g);
42int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask); 42int gm20b_gr_tpc_disable_override(struct gk20a *g, u32 mask);
43void gr_gm20b_set_rd_coalesce(struct gk20a *g, u32 data); 43void gr_gm20b_set_rd_coalesce(struct gk20a *g, u32 data);
44 44void gm20a_gr_disable_rd_coalesce(struct gk20a *g);
45void gr_gm20b_init_gpc_mmu(struct gk20a *g);
46void gr_gm20b_bundle_cb_defaults(struct gk20a *g);
47void gr_gm20b_cb_size_default(struct gk20a *g);
48int gr_gm20b_calc_global_ctx_buffer_size(struct gk20a *g);
49void gr_gm20b_commit_global_bundle_cb(struct gk20a *g,
50 struct channel_ctx_gk20a *ch_ctx,
51 u64 addr, u64 size, bool patch);
52int gr_gm20b_commit_global_cb_manager(struct gk20a *g,
53 struct channel_gk20a *c, bool patch);
54void gr_gm20b_commit_global_pagepool(struct gk20a *g,
55 struct channel_ctx_gk20a *ch_ctx,
56 u64 addr, u32 size, bool patch);
57int gr_gm20b_handle_sw_method(struct gk20a *g, u32 addr,
58 u32 class_num, u32 offset, u32 data);
59void gr_gm20b_set_alpha_circular_buffer_size(struct gk20a *g, u32 data);
60void gr_gm20b_set_circular_buffer_size(struct gk20a *g, u32 data);
61void gr_gm20b_set_hww_esr_report_mask(struct gk20a *g);
62bool gr_gm20b_is_valid_class(struct gk20a *g, u32 class_num);
63bool gr_gm20b_is_valid_gfx_class(struct gk20a *g, u32 class_num);
64bool gr_gm20b_is_valid_compute_class(struct gk20a *g, u32 class_num);
65void gr_gm20b_init_sm_dsm_reg_info(void);
66void gr_gm20b_get_sm_dsm_perf_regs(struct gk20a *g,
67 u32 *num_sm_dsm_perf_regs,
68 u32 **sm_dsm_perf_regs,
69 u32 *perf_register_stride);
70void gr_gm20b_get_sm_dsm_perf_ctrl_regs(struct gk20a *g,
71 u32 *num_sm_dsm_perf_ctrl_regs,
72 u32 **sm_dsm_perf_ctrl_regs,
73 u32 *ctrl_register_stride);
74u32 gr_gm20b_get_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
75void gr_gm20b_set_gpc_tpc_mask(struct gk20a *g, u32 gpc_index);
76void gr_gm20b_load_tpc_mask(struct gk20a *g);
77void gr_gm20b_program_sm_id_numbering(struct gk20a *g,
78 u32 gpc, u32 tpc, u32 smid);
79int gr_gm20b_load_smid_config(struct gk20a *g);
80int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base,
81 struct gk20a_ctxsw_ucode_segments *segments, u32 reg_offset);
82bool gr_gm20b_is_tpc_addr(struct gk20a *g, u32 addr);
83u32 gr_gm20b_get_tpc_num(struct gk20a *g, u32 addr);
84int gr_gm20b_load_ctxsw_ucode(struct gk20a *g);
85int gr_gm20b_load_ctxsw_ucode(struct gk20a *g);
86void gr_gm20b_detect_sm_arch(struct gk20a *g);
87u32 gr_gm20b_pagepool_default_size(struct gk20a *g);
88int gr_gm20b_alloc_gr_ctx(struct gk20a *g,
89 struct gr_ctx_desc **gr_ctx, struct vm_gk20a *vm,
90 u32 class,
91 u32 flags);
92void gr_gm20b_update_ctxsw_preemption_mode(struct gk20a *g,
93 struct channel_ctx_gk20a *ch_ctx,
94 struct nvgpu_mem *mem);
95int gr_gm20b_dump_gr_status_regs(struct gk20a *g,
96 struct gk20a_debug_output *o);
97int gr_gm20b_update_pc_sampling(struct channel_gk20a *c,
98 bool enable);
99u32 gr_gm20b_get_fbp_en_mask(struct gk20a *g);
100u32 gr_gm20b_get_max_ltc_per_fbp(struct gk20a *g);
101u32 gr_gm20b_get_max_lts_per_ltc(struct gk20a *g);
102u32 *gr_gm20b_rop_l2_en_mask(struct gk20a *g);
103u32 gr_gm20b_get_max_fbps_count(struct gk20a *g);
104void gr_gm20b_init_cyclestats(struct gk20a *g);
105void gr_gm20b_enable_cde_in_fecs(struct gk20a *g, struct nvgpu_mem *mem);
106void gr_gm20b_bpt_reg_info(struct gk20a *g, struct warpstate *w_state);
107void gr_gm20b_get_access_map(struct gk20a *g,
108 u32 **whitelist, int *num_entries);
109int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc);
110int gm20b_gr_update_sm_error_state(struct gk20a *g,
111 struct channel_gk20a *ch, u32 sm_id,
112 struct nvgpu_dbg_gpu_sm_error_state_record *sm_error_state);
113int gm20b_gr_clear_sm_error_state(struct gk20a *g,
114 struct channel_gk20a *ch, u32 sm_id);
115int gr_gm20b_get_preemption_mode_flags(struct gk20a *g,
116 struct nvgpu_preemption_modes_rec *preemption_modes_rec);
117int gm20b_gr_fuse_override(struct gk20a *g);
118bool gr_gm20b_is_ltcs_ltss_addr(struct gk20a *g, u32 addr);
119bool gr_gm20b_is_ltcn_ltss_addr(struct gk20a *g, u32 addr);
120void gr_gm20b_split_lts_broadcast_addr(struct gk20a *g, u32 addr,
121 u32 *priv_addr_table,
122 u32 *priv_addr_table_index);
123void gr_gm20b_split_ltc_broadcast_addr(struct gk20a *g, u32 addr,
124 u32 *priv_addr_table,
125 u32 *priv_addr_table_index);
126void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm,
127 u32 global_esr);
45#endif 128#endif
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index aa953ca5..b77f10d2 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -27,6 +27,7 @@
27#include "gk20a/priv_ring_gk20a.h" 27#include "gk20a/priv_ring_gk20a.h"
28#include "gk20a/regops_gk20a.h" 28#include "gk20a/regops_gk20a.h"
29#include "gk20a/pmu_gk20a.h" 29#include "gk20a/pmu_gk20a.h"
30#include "gk20a/gr_gk20a.h"
30 31
31#include "ltc_gm20b.h" 32#include "ltc_gm20b.h"
32#include "gr_gm20b.h" 33#include "gr_gm20b.h"
@@ -170,6 +171,118 @@ static const struct gpu_ops gm20b_ops = {
170 .isr_stall = gk20a_ce2_isr, 171 .isr_stall = gk20a_ce2_isr,
171 .isr_nonstall = gk20a_ce2_nonstall_isr, 172 .isr_nonstall = gk20a_ce2_nonstall_isr,
172 }, 173 },
174 .gr = {
175 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
176 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
177 .cb_size_default = gr_gm20b_cb_size_default,
178 .calc_global_ctx_buffer_size =
179 gr_gm20b_calc_global_ctx_buffer_size,
180 .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb,
181 .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb,
182 .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager,
183 .commit_global_pagepool = gr_gm20b_commit_global_pagepool,
184 .handle_sw_method = gr_gm20b_handle_sw_method,
185 .set_alpha_circular_buffer_size =
186 gr_gm20b_set_alpha_circular_buffer_size,
187 .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size,
188 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
189 .is_valid_class = gr_gm20b_is_valid_class,
190 .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class,
191 .is_valid_compute_class = gr_gm20b_is_valid_compute_class,
192 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
193 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
194 .init_fs_state = gr_gm20b_init_fs_state,
195 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
196 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
197 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
198 .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,
199 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
200 .free_channel_ctx = gk20a_free_channel_ctx,
201 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
202 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
203 .get_zcull_info = gr_gk20a_get_zcull_info,
204 .is_tpc_addr = gr_gm20b_is_tpc_addr,
205 .get_tpc_num = gr_gm20b_get_tpc_num,
206 .detect_sm_arch = gr_gm20b_detect_sm_arch,
207 .add_zbc_color = gr_gk20a_add_zbc_color,
208 .add_zbc_depth = gr_gk20a_add_zbc_depth,
209 .zbc_set_table = gk20a_gr_zbc_set_table,
210 .zbc_query_table = gr_gk20a_query_zbc,
211 .pmu_save_zbc = gk20a_pmu_save_zbc,
212 .add_zbc = gr_gk20a_add_zbc,
213 .pagepool_default_size = gr_gm20b_pagepool_default_size,
214 .init_ctx_state = gr_gk20a_init_ctx_state,
215 .alloc_gr_ctx = gr_gm20b_alloc_gr_ctx,
216 .free_gr_ctx = gr_gk20a_free_gr_ctx,
217 .update_ctxsw_preemption_mode =
218 gr_gm20b_update_ctxsw_preemption_mode,
219 .dump_gr_regs = gr_gm20b_dump_gr_status_regs,
220 .update_pc_sampling = gr_gm20b_update_pc_sampling,
221 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
222 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
223 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
224 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
225 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
226 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
227 .wait_empty = gr_gk20a_wait_idle,
228 .init_cyclestats = gr_gm20b_init_cyclestats,
229 .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
230 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
231 .bpt_reg_info = gr_gm20b_bpt_reg_info,
232 .get_access_map = gr_gm20b_get_access_map,
233 .handle_fecs_error = gk20a_gr_handle_fecs_error,
234 .handle_sm_exception = gr_gk20a_handle_sm_exception,
235 .handle_tex_exception = gr_gk20a_handle_tex_exception,
236 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
237 .enable_exceptions = gk20a_gr_enable_exceptions,
238 .get_lrf_tex_ltc_dram_override = NULL,
239 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
240 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
241 .record_sm_error_state = gm20b_gr_record_sm_error_state,
242 .update_sm_error_state = gm20b_gr_update_sm_error_state,
243 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
244 .suspend_contexts = gr_gk20a_suspend_contexts,
245 .resume_contexts = gr_gk20a_resume_contexts,
246 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
247 .fuse_override = gm20b_gr_fuse_override,
248 .init_sm_id_table = gr_gk20a_init_sm_id_table,
249 .load_smid_config = gr_gm20b_load_smid_config,
250 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
251 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
252 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
253 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
254 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
255 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
256 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
257 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
258 .commit_inst = gr_gk20a_commit_inst,
259 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
260 .write_pm_ptr = gr_gk20a_write_pm_ptr,
261 .init_elcg_mode = gr_gk20a_init_elcg_mode,
262 .load_tpc_mask = gr_gm20b_load_tpc_mask,
263 .inval_icache = gr_gk20a_inval_icache,
264 .trigger_suspend = gr_gk20a_trigger_suspend,
265 .wait_for_pause = gr_gk20a_wait_for_pause,
266 .resume_from_pause = gr_gk20a_resume_from_pause,
267 .clear_sm_errors = gr_gk20a_clear_sm_errors,
268 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
269 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
270 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
271 .suspend_single_sm = gk20a_gr_suspend_single_sm,
272 .suspend_all_sms = gk20a_gr_suspend_all_sms,
273 .resume_single_sm = gk20a_gr_resume_single_sm,
274 .resume_all_sms = gk20a_gr_resume_all_sms,
275 .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr,
276 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
277 .get_sm_no_lock_down_hww_global_esr_mask =
278 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
279 .lock_down_sm = gk20a_gr_lock_down_sm,
280 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
281 .clear_sm_hww = gm20b_gr_clear_sm_hww,
282 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
283 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
284 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
285 },
173 .fb = { 286 .fb = {
174 .reset = fb_gk20a_reset, 287 .reset = fb_gk20a_reset,
175 .init_hw = gk20a_fb_init_hw, 288 .init_hw = gk20a_fb_init_hw,
@@ -448,6 +561,7 @@ int gm20b_init_hal(struct gk20a *g)
448 561
449 gops->ltc = gm20b_ops.ltc; 562 gops->ltc = gm20b_ops.ltc;
450 gops->ce2 = gm20b_ops.ce2; 563 gops->ce2 = gm20b_ops.ce2;
564 gops->gr = gm20b_ops.gr;
451 gops->fb = gm20b_ops.fb; 565 gops->fb = gm20b_ops.fb;
452 gops->clock_gating = gm20b_ops.clock_gating; 566 gops->clock_gating = gm20b_ops.clock_gating;
453 gops->fifo = gm20b_ops.fifo; 567 gops->fifo = gm20b_ops.fifo;
@@ -538,6 +652,8 @@ int gm20b_init_hal(struct gk20a *g)
538 652
539 gops->pmu.init_wpr_region = gm20b_pmu_init_acr; 653 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
540 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; 654 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
655
656 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
541 } else { 657 } else {
542 /* Inherit from gk20a */ 658 /* Inherit from gk20a */
543 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported; 659 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
@@ -547,14 +663,14 @@ int gm20b_init_hal(struct gk20a *g)
547 663
548 gops->pmu.load_lsfalcon_ucode = NULL; 664 gops->pmu.load_lsfalcon_ucode = NULL;
549 gops->pmu.init_wpr_region = NULL; 665 gops->pmu.init_wpr_region = NULL;
666
667 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
550 } 668 }
551 669
552 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); 670 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
553 g->pmu_lsf_pmu_wpr_init_done = 0; 671 g->pmu_lsf_pmu_wpr_init_done = 0;
554 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; 672 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
555 673
556 gm20b_init_gr(g);
557
558 gm20b_init_uncompressed_kind_map(); 674 gm20b_init_uncompressed_kind_map();
559 gm20b_init_kind_attr(); 675 gm20b_init_kind_attr();
560 676
generated by cgit v1.2.2 (git 2.25.0) at 2024-07-04 21:44:38 -0400