diff options
author | Supriya <ssharatkumar@nvidia.com> | 2015-08-07 03:02:32 -0400 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2015-08-21 13:59:07 -0400 |
commit | 3fba1e929ba17531f88809cbc12212cedaed015b (patch) | |
tree | c83dc5eb3b5df954fa52eab15df3b5d79efc08cf /drivers/gpu/nvgpu/gm20b | |
parent | e44e67333bb835c54a2a66835a13498d4080893f (diff) |
gpu: nvgpu: Fix NS boot transcfg
Bug 1667322
Accommodate for transcfg address change
Change-Id: I7054202b8ce3be1a3fbfe0465e662be6f9740eb3
Signed-off-by: Supriya <ssharatkumar@nvidia.com>
Reviewed-on: http://git-master/r/780326
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.c | 33 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/acr_gm20b.h | 1 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 2 |
3 files changed, 36 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c index 3a19d6b6..152b9637 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c | |||
@@ -1213,6 +1213,39 @@ static int bl_bootstrap(struct pmu_gk20a *pmu, | |||
1213 | return 0; | 1213 | return 0; |
1214 | } | 1214 | } |
1215 | 1215 | ||
1216 | int gm20b_init_nspmu_setup_hw1(struct gk20a *g) | ||
1217 | { | ||
1218 | struct pmu_gk20a *pmu = &g->pmu; | ||
1219 | int err = 0; | ||
1220 | |||
1221 | gk20a_dbg_fn(""); | ||
1222 | |||
1223 | mutex_lock(&pmu->isr_mutex); | ||
1224 | pmu_reset(pmu); | ||
1225 | pmu->isr_enabled = true; | ||
1226 | mutex_unlock(&pmu->isr_mutex); | ||
1227 | |||
1228 | /* setup apertures - virtual */ | ||
1229 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
1230 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
1231 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
1232 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
1233 | /* setup apertures - physical */ | ||
1234 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
1235 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1236 | pwr_fbif_transcfg_target_local_fb_f()); | ||
1237 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
1238 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1239 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
1240 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
1241 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
1242 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
1243 | |||
1244 | err = g->ops.pmu.pmu_nsbootstrap(pmu); | ||
1245 | |||
1246 | return err; | ||
1247 | } | ||
1248 | |||
1216 | static int gm20b_init_pmu_setup_hw1(struct gk20a *g, | 1249 | static int gm20b_init_pmu_setup_hw1(struct gk20a *g, |
1217 | struct flcn_bl_dmem_desc *desc, u32 bl_sz) | 1250 | struct flcn_bl_dmem_desc *desc, u32 bl_sz) |
1218 | { | 1251 | { |
diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h index bd3b633a..fd9cf2ec 100644 --- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.h | |||
@@ -407,4 +407,5 @@ int gm20b_pmu_setup_sw(struct gk20a *g); | |||
407 | int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt); | 407 | int pmu_exec_gen_bl(struct gk20a *g, void *desc, u8 b_wait_for_halt); |
408 | int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_us); | 408 | int pmu_wait_for_halt(struct gk20a *g, unsigned int timeout_us); |
409 | int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); | 409 | int clear_halt_interrupt_status(struct gk20a *g, unsigned int timeout); |
410 | int gm20b_init_nspmu_setup_hw1(struct gk20a *g); | ||
410 | #endif /*__ACR_GM20B_H_*/ | 411 | #endif /*__ACR_GM20B_H_*/ |
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index c3aad72b..813bb16c 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -291,6 +291,8 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops) | |||
291 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; | 291 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; |
292 | } else { | 292 | } else { |
293 | gk20a_init_pmu_ops(gops); | 293 | gk20a_init_pmu_ops(gops); |
294 | gops->pmu.pmu_setup_hw_and_bootstrap = | ||
295 | gm20b_init_nspmu_setup_hw1; | ||
294 | gops->pmu.load_lsfalcon_ucode = NULL; | 296 | gops->pmu.load_lsfalcon_ucode = NULL; |
295 | gops->pmu.init_wpr_region = NULL; | 297 | gops->pmu.init_wpr_region = NULL; |
296 | } | 298 | } |