diff options
author | Mayank Kaushik <mkaushik@nvidia.com> | 2014-09-17 21:11:45 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:11:57 -0400 |
commit | 3d313d06570dcb28bba73247a2c0fc52bec56af0 (patch) | |
tree | 69c98965a8f5833c791069d6bd1442075e8e6a2e /drivers/gpu/nvgpu/gm20b | |
parent | 50d76e9b91a4b4b03bea5f92a7a1af452ce7c6f9 (diff) |
gpu: nvgpu: gm20b: halify tpc lookup
Since the number of TPCs is different between GM20B and GK20a,
the function to look up the number of TPCs needs to be halified.
Change-Id: I19dab9a7105814f86c08c92283a0bb70abb6aa00
Signed-off-by: Mayank Kaushik <mkaushik@nvidia.com>
Reviewed-on: http://git-master/r/500064
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 33 |
1 files changed, 33 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index 8a3de4e8..835ff6bf 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -614,6 +614,37 @@ static int gr_gm20b_load_ctxsw_ucode_segments(struct gk20a *g, u64 addr_base, | |||
614 | return 0; | 614 | return 0; |
615 | } | 615 | } |
616 | 616 | ||
617 | static bool gr_gm20b_is_tpc_addr_shared(u32 addr) | ||
618 | { | ||
619 | return (addr >= proj_tpc_in_gpc_shared_base_v()) && | ||
620 | (addr < (proj_tpc_in_gpc_shared_base_v() + | ||
621 | proj_tpc_in_gpc_stride_v())); | ||
622 | } | ||
623 | |||
624 | static bool gr_gm20b_is_tpc_addr(u32 addr) | ||
625 | { | ||
626 | return ((addr >= proj_tpc_in_gpc_base_v()) && | ||
627 | (addr < proj_tpc_in_gpc_base_v() + | ||
628 | (proj_scal_litter_num_tpc_per_gpc_v() * | ||
629 | proj_tpc_in_gpc_stride_v()))) | ||
630 | || gr_gm20b_is_tpc_addr_shared(addr); | ||
631 | } | ||
632 | |||
633 | static u32 gr_gm20b_get_tpc_num(u32 addr) | ||
634 | { | ||
635 | u32 i, start; | ||
636 | u32 num_tpcs = proj_scal_litter_num_tpc_per_gpc_v(); | ||
637 | |||
638 | for (i = 0; i < num_tpcs; i++) { | ||
639 | start = proj_tpc_in_gpc_base_v() + | ||
640 | (i * proj_tpc_in_gpc_stride_v()); | ||
641 | if ((addr >= start) && | ||
642 | (addr < (start + proj_tpc_in_gpc_stride_v()))) | ||
643 | return i; | ||
644 | } | ||
645 | return 0; | ||
646 | } | ||
647 | |||
617 | #ifdef CONFIG_TEGRA_ACR | 648 | #ifdef CONFIG_TEGRA_ACR |
618 | static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g) | 649 | static void gr_gm20b_load_gpccs_with_bootloader(struct gk20a *g) |
619 | { | 650 | { |
@@ -748,4 +779,6 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
748 | gops->gr.free_obj_ctx = gk20a_free_obj_ctx; | 779 | gops->gr.free_obj_ctx = gk20a_free_obj_ctx; |
749 | gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull; | 780 | gops->gr.bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull; |
750 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; | 781 | gops->gr.get_zcull_info = gr_gk20a_get_zcull_info; |
782 | gops->gr.is_tpc_addr = gr_gm20b_is_tpc_addr; | ||
783 | gops->gr.get_tpc_num = gr_gm20b_get_tpc_num; | ||
751 | } | 784 | } |