diff options
author | Alex Frid <afrid@nvidia.com> | 2017-08-04 23:03:22 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-14 18:55:37 -0400 |
commit | 32c6a81258daf155a382526637c84925dc52022c (patch) | |
tree | 47975566554f7b26a706695f2ceebca13d9a2069 /drivers/gpu/nvgpu/gm20b | |
parent | 959c02d6757c3c40748f7d2db1515885a5066a12 (diff) |
gpu: nvgpu: Update GM20B GPCPLL rev C1 parameters
- Set GM20B GPCPLL rev C1 DFS coefficients.
- Updated VCO control setting
- Decreased output frequency minimum to 76.8 MHz
Bug 1971441
Change-Id: Ie1fa04db11d9cd76db0424acd9f24c02c6e6054a
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1533493
(cherry picked from commit cc495b86ad97a0a713fd46f74a4fd6d17336ff02)
Reviewed-on: https://git-master.nvidia.com/r/1538242
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 027d4fb6..81f8aec0 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -59,15 +59,15 @@ static struct pll_parms gpc_pll_params_b1 = { | |||
59 | }; | 59 | }; |
60 | 60 | ||
61 | static struct pll_parms gpc_pll_params_c1 = { | 61 | static struct pll_parms gpc_pll_params_c1 = { |
62 | 128000, 2600000, /* freq */ | 62 | 76800, 2600000, /* freq */ |
63 | 1300000, 2600000, /* vco */ | 63 | 1300000, 2600000, /* vco */ |
64 | 19200, 38400, /* u */ | 64 | 19200, 38400, /* u */ |
65 | 1, 255, /* M */ | 65 | 1, 255, /* M */ |
66 | 8, 255, /* N */ | 66 | 8, 255, /* N */ |
67 | 1, 31, /* PL */ | 67 | 1, 31, /* PL */ |
68 | 0, 0, /* DFS_COEFF */ | 68 | -172550, 195374, /* DFS_COEFF */ |
69 | 0, 0, /* ADC char coeff - to be read from fuses */ | 69 | 0, 0, /* ADC char coeff - to be read from fuses */ |
70 | 0x7 << 3, /* vco control in NA mode */ | 70 | (0x1 << 3) | 0x7, /* vco control in NA mode */ |
71 | 500, /* Locking and ramping timeout */ | 71 | 500, /* Locking and ramping timeout */ |
72 | 40, /* Lock delay in NA mode */ | 72 | 40, /* Lock delay in NA mode */ |
73 | 5, /* IDDQ mode exit delay */ | 73 | 5, /* IDDQ mode exit delay */ |