diff options
author | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-12-20 18:14:16 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-04 04:44:24 -0500 |
commit | 2a95a288b285b0eff16a8825298c416d185693fb (patch) | |
tree | 8040b60aa5761b638f08cc1032feb0f729ed57ae /drivers/gpu/nvgpu/gm20b | |
parent | fef7083e516ff6da4681ea8aaeedc114c6f2c821 (diff) |
gpu: nvgpu: Check reference clock before use
We use GPU reference clock as a divider. Check before division that
reference clock is not zero.
Change-Id: Ie453a78b422b2e740daeb7c12ce5b06faa52ba76
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/1275743
GVS: Gerrit_Virtual_Submit
Reviewed-by: Thomas Fleury <tfleury@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 5 |
1 files changed, 5 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index 906e805a..3fa5c1d3 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1158,6 +1158,11 @@ static int gm20b_init_gpc_pll(struct gk20a *g) | |||
1158 | 1158 | ||
1159 | clk->gpc_pll.id = GK20A_GPC_PLL; | 1159 | clk->gpc_pll.id = GK20A_GPC_PLL; |
1160 | clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; | 1160 | clk->gpc_pll.clk_in = clk_get_rate(ref) / KHZ; |
1161 | if (clk->gpc_pll.clk_in == 0) { | ||
1162 | gk20a_err(dev_from_gk20a(g), | ||
1163 | "GPCPLL reference clock is zero"); | ||
1164 | return -EINVAL; | ||
1165 | } | ||
1161 | 1166 | ||
1162 | gm20b_calc_dvfs_safe_max_freq(c); | 1167 | gm20b_calc_dvfs_safe_max_freq(c); |
1163 | clk->gpc_pll.PL = (dvfs_safe_max_freq == 0) ? 0 : | 1168 | clk->gpc_pll.PL = (dvfs_safe_max_freq == 0) ? 0 : |