summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gm20b
diff options
context:
space:
mode:
authorDeepak Nibade <dnibade@nvidia.com>2018-09-04 07:07:33 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-09-05 23:41:36 -0400
commit2998ab4e0a0b19da1332b82d779bd17b4e284b38 (patch)
treee86e3201c1920f8cb0afecdb6e21f9c0bf8de366 /drivers/gpu/nvgpu/gm20b
parent2b2bde04e14135cae5f7433c755e6b8d70f88abb (diff)
gpu: nvgpu: remove unused regops HALs
Below regops HALs are not being called from anywhere, so remove them gops.regops.get_runcontrol_whitelist_ranges() gops.regops.get_runcontrol_whitelist_ranges_count() gops.regops.get_qctl_whitelist_ranges() gops.regops.get_qctl_whitelist_ranges_count() HAL gops.regops.apply_smpc_war() is unimplemented for all the chips, and it was originally only needed for gk20a which is not unsupported So remove this HAL and its call too Jira NVGPU-620 Change-Id: Ia2c74883cd647a2e94ee740ffd040a40c442b939 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1813106 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c8
-rw-r--r--drivers/gpu/nvgpu/gm20b/regops_gm20b.c46
2 files changed, 0 insertions, 54 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 2f90512e..ca7081cf 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -574,16 +574,8 @@ static const struct gpu_ops gm20b_ops = {
574 .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist, 574 .get_runcontrol_whitelist = gm20b_get_runcontrol_whitelist,
575 .get_runcontrol_whitelist_count = 575 .get_runcontrol_whitelist_count =
576 gm20b_get_runcontrol_whitelist_count, 576 gm20b_get_runcontrol_whitelist_count,
577 .get_runcontrol_whitelist_ranges =
578 gm20b_get_runcontrol_whitelist_ranges,
579 .get_runcontrol_whitelist_ranges_count =
580 gm20b_get_runcontrol_whitelist_ranges_count,
581 .get_qctl_whitelist = gm20b_get_qctl_whitelist, 577 .get_qctl_whitelist = gm20b_get_qctl_whitelist,
582 .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count, 578 .get_qctl_whitelist_count = gm20b_get_qctl_whitelist_count,
583 .get_qctl_whitelist_ranges = gm20b_get_qctl_whitelist_ranges,
584 .get_qctl_whitelist_ranges_count =
585 gm20b_get_qctl_whitelist_ranges_count,
586 .apply_smpc_war = gm20b_apply_smpc_war,
587 }, 579 },
588 .mc = { 580 .mc = {
589 .intr_mask = mc_gk20a_intr_mask, 581 .intr_mask = mc_gk20a_intr_mask,
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
index e23a0a62..ab865b68 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
@@ -23,12 +23,9 @@
23 */ 23 */
24 24
25#include "gk20a/gk20a.h" 25#include "gk20a/gk20a.h"
26#include "gk20a/dbg_gpu_gk20a.h"
27#include "gk20a/regops_gk20a.h" 26#include "gk20a/regops_gk20a.h"
28#include "regops_gm20b.h" 27#include "regops_gm20b.h"
29 28
30#include <nvgpu/bsearch.h>
31
32static const struct regop_offset_range gm20b_global_whitelist_ranges[] = { 29static const struct regop_offset_range gm20b_global_whitelist_ranges[] = {
33 { 0x00001a00, 3 }, 30 { 0x00001a00, 3 },
34 { 0x0000259c, 1 }, 31 { 0x0000259c, 1 },
@@ -366,29 +363,12 @@ static const u32 gm20b_runcontrol_whitelist[] = {
366static const u64 gm20b_runcontrol_whitelist_count = 363static const u64 gm20b_runcontrol_whitelist_count =
367 ARRAY_SIZE(gm20b_runcontrol_whitelist); 364 ARRAY_SIZE(gm20b_runcontrol_whitelist);
368 365
369static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = {
370 { 0x00419e10, 1 },
371 { 0x0041c610, 1 },
372 { 0x0041ce10, 1 },
373 { 0x00501e10, 1 },
374 { 0x00504610, 1 },
375 { 0x00504e10, 1 },
376};
377static const u64 gm20b_runcontrol_whitelist_ranges_count =
378 ARRAY_SIZE(gm20b_runcontrol_whitelist_ranges);
379
380
381/* quad ctl */ 366/* quad ctl */
382static const u32 gm20b_qctl_whitelist[] = { 367static const u32 gm20b_qctl_whitelist[] = {
383}; 368};
384static const u64 gm20b_qctl_whitelist_count = 369static const u64 gm20b_qctl_whitelist_count =
385 ARRAY_SIZE(gm20b_qctl_whitelist); 370 ARRAY_SIZE(gm20b_qctl_whitelist);
386 371
387static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = {
388};
389static const u64 gm20b_qctl_whitelist_ranges_count =
390 ARRAY_SIZE(gm20b_qctl_whitelist_ranges);
391
392const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) 372const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void)
393{ 373{
394 return gm20b_global_whitelist_ranges; 374 return gm20b_global_whitelist_ranges;
@@ -419,16 +399,6 @@ u64 gm20b_get_runcontrol_whitelist_count(void)
419 return gm20b_runcontrol_whitelist_count; 399 return gm20b_runcontrol_whitelist_count;
420} 400}
421 401
422const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void)
423{
424 return gm20b_runcontrol_whitelist_ranges;
425}
426
427u64 gm20b_get_runcontrol_whitelist_ranges_count(void)
428{
429 return gm20b_runcontrol_whitelist_ranges_count;
430}
431
432const u32 *gm20b_get_qctl_whitelist(void) 402const u32 *gm20b_get_qctl_whitelist(void)
433{ 403{
434 return gm20b_qctl_whitelist; 404 return gm20b_qctl_whitelist;
@@ -438,19 +408,3 @@ u64 gm20b_get_qctl_whitelist_count(void)
438{ 408{
439 return gm20b_qctl_whitelist_count; 409 return gm20b_qctl_whitelist_count;
440} 410}
441
442const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void)
443{
444 return gm20b_qctl_whitelist_ranges;
445}
446
447u64 gm20b_get_qctl_whitelist_ranges_count(void)
448{
449 return gm20b_qctl_whitelist_ranges_count;
450}
451
452int gm20b_apply_smpc_war(struct dbg_session_gk20a *dbg_s)
453{
454 /* Not needed on gm20b */
455 return 0;
456}