gpu: nvgpu: Remove mm.get_iova_addr

Remove the mm.get_iova_addr() HAL and replace it with a new HAL
called mm.gpu_phys_addr(). This new HAL provides the real phys
address that should be passed to the GPU from a physical address
obtained from a scatter list. It also provides a mechanism by
which the HAL code can add extra bits to a GPU physical address
based on the attributes passed in. This is necessary during GMMU
page table programming.

Also remove the flags argument from the various address functions.
This flag was used for adding an IO coherence bit to the GPU
physical address which is not supported.

JIRA NVGPU-30

Change-Id: I69af5b1c6bd905c4077c26c098fac101c6b41a33
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530864
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

4 files changed, 6 insertions, 4 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
index 0d69b5da..4fa1b313 100644
--- a/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/acr_gm20b.c
@@ -1081,7 +1081,7 @@ static int gm20b_bootstrap_hs_flcn(struct gk20a *g)
         u32 *acr_ucode_header_t210_load;
         u32 *acr_ucode_data_t210_load;
 
-        start = g->ops.mm.get_iova_addr(g, acr->ucode_blob.priv.sgt->sgl, 0);
+        start = nvgpu_mem_get_addr(g, &acr->ucode_blob);
         size = acr->ucode_blob.size;
 
         gm20b_dbg_pmu("");
diff --git a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
index 6fef01ea..74c56487 100644
--- a/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/ltc_gm20b.c
@@ -401,8 +401,8 @@ void gm20b_ltc_init_cbc(struct gk20a *g, struct gr_gk20a *gr)
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL))
                 compbit_store_iova = gk20a_mem_phys(&gr->compbit_store.mem);
         else
-                compbit_store_iova = g->ops.mm.get_iova_addr(g,
-                                gr->compbit_store.mem.priv.sgt->sgl, 0);
+                compbit_store_iova = nvgpu_mem_get_addr(g,
+                                                        &gr->compbit_store.mem);
 
         compbit_base_post_divide64 = compbit_store_iova >>
                 ltc_ltcs_ltss_cbc_base_alignment_shift_v();
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index d436e985..bbcd6314 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -80,7 +80,6 @@ void gm20b_init_mm(struct gpu_ops *gops)
         gops->mm.get_big_page_sizes = gm20b_mm_get_big_page_sizes;
         gops->mm.get_default_big_page_size = gm20b_mm_get_default_big_page_size;
         gops->mm.gpu_phys_addr = gm20b_gpu_phys_addr;
-        gops->mm.get_iova_addr = gk20a_mm_iova_addr;
         gops->mm.get_physical_addr_bits = gk20a_mm_get_physical_addr_bits;
         gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels;
         gops->mm.init_pdb = gk20a_mm_init_pdb;
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
index 99d6c161..2bb29ea8 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.h
@@ -20,6 +20,9 @@ struct gk20a;
 #define PDE_ADDR_START(x, y)    ((x) &  ~((0x1UL << (y)) - 1))
 #define PDE_ADDR_END(x, y)      ((x) | ((0x1UL << (y)) - 1))
 
+u64 gm20b_gpu_phys_addr(struct gk20a *g,
+                        struct nvgpu_gmmu_attrs *attrs, u64 phys);
+
 void gm20b_init_mm(struct gpu_ops *gops);
 int gm20b_mm_mmu_vpr_info_fetch(struct gk20a *g);
 #endif