diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2017-03-29 04:58:15 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-03-30 15:36:15 -0400 |
commit | 1ca4c5f069f8b055248aab61619c9a2490b1fe9c (patch) | |
tree | 1d0ba3accc2a86f346da9d73ad9107d90e57cb6e /drivers/gpu/nvgpu/gm20b | |
parent | caee1441b899383a10b2848e43dc4255f8d5342f (diff) |
gpu: nvgpu: check return value of mutex_init in clk code
- check return value of nvgpu_mutex_init in
clk_gk20a.c/clk_gm20b.c/clk_gp106.c
- add corresponding nvgpu_mutex_destroy calls
Jira NVGPU-13
Change-Id: If6ddc2c924e1ab13274b857f904859033722479a
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1321293
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 26 |
1 files changed, 20 insertions, 6 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index d6eec0a5..451dd7b6 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -1122,16 +1122,23 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1122 | struct clk_gk20a *clk = &g->clk; | 1122 | struct clk_gk20a *clk = &g->clk; |
1123 | unsigned long safe_rate; | 1123 | unsigned long safe_rate; |
1124 | struct clk *ref, *c; | 1124 | struct clk *ref, *c; |
1125 | int err; | ||
1125 | 1126 | ||
1126 | gk20a_dbg_fn(""); | 1127 | gk20a_dbg_fn(""); |
1127 | 1128 | ||
1129 | err = nvgpu_mutex_init(&clk->clk_mutex); | ||
1130 | if (err) | ||
1131 | return err; | ||
1132 | |||
1128 | if (clk->sw_ready) { | 1133 | if (clk->sw_ready) { |
1129 | gk20a_dbg_fn("skip init"); | 1134 | gk20a_dbg_fn("skip init"); |
1130 | return 0; | 1135 | return 0; |
1131 | } | 1136 | } |
1132 | 1137 | ||
1133 | if (!gk20a_clk_get(g)) | 1138 | if (!gk20a_clk_get(g)) { |
1134 | return -EINVAL; | 1139 | err = -EINVAL; |
1140 | goto fail; | ||
1141 | } | ||
1135 | 1142 | ||
1136 | /* | 1143 | /* |
1137 | * On Tegra GPU clock exposed to frequency governor is a shared user on | 1144 | * On Tegra GPU clock exposed to frequency governor is a shared user on |
@@ -1149,7 +1156,8 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1149 | if (IS_ERR(ref)) { | 1156 | if (IS_ERR(ref)) { |
1150 | gk20a_err(dev_from_gk20a(g), | 1157 | gk20a_err(dev_from_gk20a(g), |
1151 | "failed to get GPCPLL reference clock"); | 1158 | "failed to get GPCPLL reference clock"); |
1152 | return -EINVAL; | 1159 | err = -EINVAL; |
1160 | goto fail; | ||
1153 | } | 1161 | } |
1154 | 1162 | ||
1155 | clk->gpc_pll.id = GK20A_GPC_PLL; | 1163 | clk->gpc_pll.id = GK20A_GPC_PLL; |
@@ -1157,7 +1165,8 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1157 | if (clk->gpc_pll.clk_in == 0) { | 1165 | if (clk->gpc_pll.clk_in == 0) { |
1158 | gk20a_err(dev_from_gk20a(g), | 1166 | gk20a_err(dev_from_gk20a(g), |
1159 | "GPCPLL reference clock is zero"); | 1167 | "GPCPLL reference clock is zero"); |
1160 | return -EINVAL; | 1168 | err = -EINVAL; |
1169 | goto fail; | ||
1161 | } | 1170 | } |
1162 | 1171 | ||
1163 | safe_rate = tegra_dvfs_get_fmax_at_vmin_safe_t(c); | 1172 | safe_rate = tegra_dvfs_get_fmax_at_vmin_safe_t(c); |
@@ -1191,8 +1200,6 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1191 | } | 1200 | } |
1192 | #endif | 1201 | #endif |
1193 | 1202 | ||
1194 | nvgpu_mutex_init(&clk->clk_mutex); | ||
1195 | |||
1196 | clk->sw_ready = true; | 1203 | clk->sw_ready = true; |
1197 | 1204 | ||
1198 | gk20a_dbg_fn("done"); | 1205 | gk20a_dbg_fn("done"); |
@@ -1200,6 +1207,10 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
1200 | clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "", | 1207 | clk->gpc_pll.mode == GPC_PLL_MODE_DVFS ? " NA mode," : "", |
1201 | clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL); | 1208 | clk->gpc_pll.M, clk->gpc_pll.N, clk->gpc_pll.PL); |
1202 | return 0; | 1209 | return 0; |
1210 | |||
1211 | fail: | ||
1212 | nvgpu_mutex_destroy(&clk->clk_mutex); | ||
1213 | return err; | ||
1203 | } | 1214 | } |
1204 | 1215 | ||
1205 | 1216 | ||
@@ -1587,6 +1598,9 @@ static int gm20b_suspend_clk_support(struct gk20a *g) | |||
1587 | ret = clk_disable_gpcpll(g, 1); | 1598 | ret = clk_disable_gpcpll(g, 1); |
1588 | g->clk.clk_hw_on = false; | 1599 | g->clk.clk_hw_on = false; |
1589 | nvgpu_mutex_release(&g->clk.clk_mutex); | 1600 | nvgpu_mutex_release(&g->clk.clk_mutex); |
1601 | |||
1602 | nvgpu_mutex_destroy(&g->clk.clk_mutex); | ||
1603 | |||
1590 | return ret; | 1604 | return ret; |
1591 | } | 1605 | } |
1592 | 1606 | ||