diff options
author | Alex Frid <afrid@nvidia.com> | 2014-07-25 02:18:20 -0400 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-03-18 15:10:37 -0400 |
commit | 14f47ad1f01fe7dce06081072bc8a03ea80841c2 (patch) | |
tree | 89d67a87a3ea911ee7e9a6aab1ca7f21f60c7402 /drivers/gpu/nvgpu/gm20b | |
parent | 14315a95613f7323283c70cf14d870e58b8bdb54 (diff) |
gpu: nvgpu: Update GM20b GPCPLL initial configuration
- Set initial output rate to 1/3 of VCO minimum.
- Cleared global BYPASSCTRL to get ready for enabling PLL (this
won't bring PLL out of bypass, since SEL_VCO register is cleared).
- Added debugfs nodes for BYPASSCTRL and SEL_VCO state.
Bug 1450787
Change-Id: I10b068b006b7e9fbdf7854eff0cfd5cfdc1dd546
Signed-off-by: Alex Frid <afrid@nvidia.com>
Reviewed-on: http://git-master/r/447750
GVS: Gerrit_Virtual_Submit
Reviewed-by: Hoang Pham <hopham@nvidia.com>
Tested-by: Hoang Pham <hopham@nvidia.com>
Reviewed-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Tested-by: Seshendra Gadagottu <sgadagottu@nvidia.com>
Reviewed-by: Yu-Huan Hsu <yhsu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/clk_gm20b.c | 19 |
1 files changed, 17 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c index f22d4c10..8e37047e 100644 --- a/drivers/gpu/nvgpu/gm20b/clk_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/clk_gm20b.c | |||
@@ -457,13 +457,13 @@ static int gm20b_init_clk_setup_sw(struct gk20a *g) | |||
457 | clk->gpc_pll.id = GK20A_GPC_PLL; | 457 | clk->gpc_pll.id = GK20A_GPC_PLL; |
458 | clk->gpc_pll.clk_in = ref_rate / KHZ; | 458 | clk->gpc_pll.clk_in = ref_rate / KHZ; |
459 | 459 | ||
460 | /* Decide initial frequency */ | 460 | /* Initial frequency: 1/3 VCO min (low enough to be safe at Vmin) */ |
461 | if (!initialized) { | 461 | if (!initialized) { |
462 | initialized = 1; | 462 | initialized = 1; |
463 | clk->gpc_pll.M = 1; | 463 | clk->gpc_pll.M = 1; |
464 | clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco, | 464 | clk->gpc_pll.N = DIV_ROUND_UP(gpc_pll_params.min_vco, |
465 | clk->gpc_pll.clk_in); | 465 | clk->gpc_pll.clk_in); |
466 | clk->gpc_pll.PL = 1; | 466 | clk->gpc_pll.PL = 3; |
467 | clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N; | 467 | clk->gpc_pll.freq = clk->gpc_pll.clk_in * clk->gpc_pll.N; |
468 | clk->gpc_pll.freq /= pl_to_div[clk->gpc_pll.PL]; | 468 | clk->gpc_pll.freq /= pl_to_div[clk->gpc_pll.PL]; |
469 | } | 469 | } |
@@ -482,6 +482,7 @@ static int gm20b_init_clk_setup_hw(struct gk20a *g) | |||
482 | 482 | ||
483 | gk20a_dbg_fn(""); | 483 | gk20a_dbg_fn(""); |
484 | 484 | ||
485 | /* LDIV: Div4 mode (required); both bypass and vco ratios 1:1 */ | ||
485 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); | 486 | data = gk20a_readl(g, trim_sys_gpc2clk_out_r()); |
486 | data = set_field(data, | 487 | data = set_field(data, |
487 | trim_sys_gpc2clk_out_sdiv14_m() | | 488 | trim_sys_gpc2clk_out_sdiv14_m() | |
@@ -492,6 +493,15 @@ static int gm20b_init_clk_setup_hw(struct gk20a *g) | |||
492 | trim_sys_gpc2clk_out_bypdiv_f(0)); | 493 | trim_sys_gpc2clk_out_bypdiv_f(0)); |
493 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); | 494 | gk20a_writel(g, trim_sys_gpc2clk_out_r(), data); |
494 | 495 | ||
496 | /* | ||
497 | * Clear global bypass control; PLL is still under bypass, since SEL_VCO | ||
498 | * is cleared by default. | ||
499 | */ | ||
500 | data = gk20a_readl(g, trim_sys_bypassctrl_r()); | ||
501 | data = set_field(data, trim_sys_bypassctrl_gpcpll_m(), | ||
502 | trim_sys_bypassctrl_gpcpll_vco_f()); | ||
503 | gk20a_writel(g, trim_sys_bypassctrl_r(), data); | ||
504 | |||
495 | return 0; | 505 | return 0; |
496 | } | 506 | } |
497 | 507 | ||
@@ -720,6 +730,11 @@ static int pll_reg_show(struct seq_file *s, void *data) | |||
720 | return 0; | 730 | return 0; |
721 | } | 731 | } |
722 | 732 | ||
733 | reg = gk20a_readl(g, trim_sys_bypassctrl_r()); | ||
734 | seq_printf(s, "bypassctrl = %s, ", reg ? "bypass" : "vco"); | ||
735 | reg = gk20a_readl(g, trim_sys_sel_vco_r()); | ||
736 | seq_printf(s, "sel_vco = %s, ", reg ? "vco" : "bypass"); | ||
737 | |||
723 | reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); | 738 | reg = gk20a_readl(g, trim_sys_gpcpll_cfg_r()); |
724 | seq_printf(s, "cfg = 0x%x : %s : %s\n", reg, | 739 | seq_printf(s, "cfg = 0x%x : %s : %s\n", reg, |
725 | trim_sys_gpcpll_cfg_enable_v(reg) ? "enabled" : "disabled", | 740 | trim_sys_gpcpll_cfg_enable_v(reg) ? "enabled" : "disabled", |