diff options
author | Deepak Nibade <dnibade@nvidia.com> | 2016-03-09 04:21:43 -0500 |
---|---|---|
committer | Terje Bergstrom <tbergstrom@nvidia.com> | 2016-04-19 11:07:03 -0400 |
commit | 04e45bc943e9703c26f229dfbe558d94418acbe1 (patch) | |
tree | 541c62a32055255e82cc953b79b50c8925903f12 /drivers/gpu/nvgpu/gm20b | |
parent | 9cf7e23f57d8669d99886a3c82d4997b94c35df8 (diff) |
gpu: nvgpu: support storing/reading single SM error state
Add support to store error state of single SM before
preprocessing SM exception
Error state is stored as :
struct nvgpu_dbg_gpu_sm_error_state_record {
u32 hww_global_esr;
u32 hww_warp_esr;
u64 hww_warp_esr_pc;
u32 hww_global_esr_report_mask;
u32 hww_warp_esr_report_mask;
}
Note that we can safely append new fields to above
structure in the future if required
Also, add IOCTL NVGPU_DBG_GPU_IOCTL_READ_SINGLE_SM_ERROR_STATE
to support reading SM's error state by user space
Bug 200156699
Change-Id: I9a62cb01e8a35c720b52d5d202986347706c7308
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/1120329
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 30 | ||||
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 8 |
2 files changed, 38 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index b49f2301..eeb70d76 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -31,6 +31,7 @@ | |||
31 | #include "hw_fuse_gm20b.h" | 31 | #include "hw_fuse_gm20b.h" |
32 | #include "pmu_gm20b.h" | 32 | #include "pmu_gm20b.h" |
33 | #include "acr_gm20b.h" | 33 | #include "acr_gm20b.h" |
34 | #include "hw_proj_gm20b.h" | ||
34 | 35 | ||
35 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) | 36 | static void gr_gm20b_init_gpc_mmu(struct gk20a *g) |
36 | { | 37 | { |
@@ -1190,6 +1191,34 @@ static void gr_gm20b_get_access_map(struct gk20a *g, | |||
1190 | *num_entries = ARRAY_SIZE(wl_addr_gm20b); | 1191 | *num_entries = ARRAY_SIZE(wl_addr_gm20b); |
1191 | } | 1192 | } |
1192 | 1193 | ||
1194 | static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc) | ||
1195 | { | ||
1196 | int sm_id; | ||
1197 | struct gr_gk20a *gr = &g->gr; | ||
1198 | u32 offset = proj_gpc_stride_v() * gpc + | ||
1199 | proj_tpc_in_gpc_stride_v() * tpc; | ||
1200 | |||
1201 | mutex_lock(&g->dbg_sessions_lock); | ||
1202 | |||
1203 | sm_id = gr_gpc0_tpc0_sm_cfg_sm_id_v(gk20a_readl(g, | ||
1204 | gr_gpc0_tpc0_sm_cfg_r() + offset)); | ||
1205 | |||
1206 | gr->sm_error_states[sm_id].hww_global_esr = gk20a_readl(g, | ||
1207 | gr_gpc0_tpc0_sm_hww_global_esr_r() + offset); | ||
1208 | gr->sm_error_states[sm_id].hww_warp_esr = gk20a_readl(g, | ||
1209 | gr_gpc0_tpc0_sm_hww_warp_esr_r() + offset); | ||
1210 | gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g, | ||
1211 | gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() + offset); | ||
1212 | gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g, | ||
1213 | gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset); | ||
1214 | gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g, | ||
1215 | gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset); | ||
1216 | |||
1217 | mutex_unlock(&g->dbg_sessions_lock); | ||
1218 | |||
1219 | return 0; | ||
1220 | } | ||
1221 | |||
1193 | void gm20b_init_gr(struct gpu_ops *gops) | 1222 | void gm20b_init_gr(struct gpu_ops *gops) |
1194 | { | 1223 | { |
1195 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; | 1224 | gops->gr.init_gpc_mmu = gr_gm20b_init_gpc_mmu; |
@@ -1256,4 +1285,5 @@ void gm20b_init_gr(struct gpu_ops *gops) | |||
1256 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; | 1285 | gops->gr.get_lrf_tex_ltc_dram_override = NULL; |
1257 | gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; | 1286 | gops->gr.update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode; |
1258 | gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; | 1287 | gops->gr.update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode; |
1288 | gops->gr.record_sm_error_state = gm20b_gr_record_sm_error_state; | ||
1259 | } | 1289 | } |
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index dbe54860..b796e2d3 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -2130,6 +2130,10 @@ static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_f(u32 v) | |||
2130 | { | 2130 | { |
2131 | return (v & 0xffff) << 0; | 2131 | return (v & 0xffff) << 0; |
2132 | } | 2132 | } |
2133 | static inline u32 gr_gpc0_tpc0_sm_cfg_sm_id_v(u32 r) | ||
2134 | { | ||
2135 | return (r >> 0) & 0xffff; | ||
2136 | } | ||
2133 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) | 2137 | static inline u32 gr_gpc0_tpc0_sm_arch_r(void) |
2134 | { | 2138 | { |
2135 | return 0x0050469c; | 2139 | return 0x0050469c; |
@@ -3270,6 +3274,10 @@ static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_error_none_f(void) | |||
3270 | { | 3274 | { |
3271 | return 0x0; | 3275 | return 0x0; |
3272 | } | 3276 | } |
3277 | static inline u32 gr_gpc0_tpc0_sm_hww_warp_esr_pc_r(void) | ||
3278 | { | ||
3279 | return 0x00504654; | ||
3280 | } | ||
3273 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) | 3281 | static inline u32 gr_gpc0_tpc0_sm_halfctl_ctrl_r(void) |
3274 | { | 3282 | { |
3275 | return 0x00504770; | 3283 | return 0x00504770; |