gpu: nvgpu: add HALs to mmu fault descriptors.

mmu fault information for client and gpc differ
on various chip. Add separate table for each chip
based on that change and add hal functions to access
those descriptors.

bug 2050564

Change-Id: If15a4757762569d60d4ce1a6a47b8c9a93c11cb0
Signed-off-by: Vinod G <vinodg@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1704105
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

3 files changed, 38 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
index 15612995..35a7a9e1 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.c
@@ -1,7 +1,7 @@
 /*
  * GM20B Fifo
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -223,3 +223,34 @@ void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch)
                 nvgpu_rwsem_up_read(&tsg->ch_list_lock);
         }
 }
+
+static const char * const gm20b_gpc_client_descs[] = {
+        "l1 0", "t1 0", "pe 0",
+        "l1 1", "t1 1", "pe 1",
+        "l1 2", "t1 2", "pe 2",
+        "l1 3", "t1 3", "pe 3",
+        "rast", "gcc", "gpccs",
+        "prop 0", "prop 1", "prop 2", "prop 3",
+        "l1 4", "t1 4", "pe 4",
+        "l1 5", "t1 5", "pe 5",
+        "l1 6", "t1 6", "pe 6",
+        "l1 7", "t1 7", "pe 7",
+        "l1 9", "t1 9", "pe 9",
+        "l1 10", "t1 10", "pe 10",
+        "l1 11", "t1 11", "pe 11",
+        "unknown", "unknown", "unknown", "unknown",
+        "tpccs 0", "tpccs 1", "tpccs 2",
+        "tpccs 3", "tpccs 4", "tpccs 5",
+        "tpccs 6", "tpccs 7", "tpccs 8",
+        "tpccs 9", "tpccs 10", "tpccs 11",
+};
+
+void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault)
+{
+        if (mmfault->client_id >= ARRAY_SIZE(gm20b_gpc_client_descs))
+                WARN_ON(mmfault->client_id >=
+                                ARRAY_SIZE(gm20b_gpc_client_descs));
+        else
+                mmfault->client_id_desc =
+                         gm20b_gpc_client_descs[mmfault->client_id];
+}
diff --git a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
index 8d487358..f9e1f95d 100644
--- a/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/fifo_gm20b.h
@@ -1,7 +1,7 @@
 /*
  * GM20B Fifo
  *
- * Copyright (c) 2014-2017, NVIDIA CORPORATION.  All rights reserved.
+ * Copyright (c) 2014-2018, NVIDIA CORPORATION.  All rights reserved.
  *
  * Permission is hereby granted, free of charge, to any person obtaining a
  * copy of this software and associated documentation files (the "Software"),
@@ -25,6 +25,7 @@
 #ifndef _NVHOST_GM20B_FIFO
 #define _NVHOST_GM20B_FIFO
 struct gk20a;
+struct mmu_fault_info;
 
 void channel_gm20b_bind(struct channel_gk20a *c);
 void gm20b_fifo_trigger_mmu_fault(struct gk20a *g,
@@ -35,5 +36,6 @@ void gm20b_device_info_data_parse(struct gk20a *g,
                                                 u32 *pri_base, u32 *fault_id);
 void gm20b_fifo_init_pbdma_intr_descs(struct fifo_gk20a *f);
 void gm20b_fifo_tsg_verify_status_ctx_reload(struct channel_gk20a *ch);
+void gm20b_fifo_get_mmu_fault_gpc_desc(struct mmu_fault_info *mmfault);
 
 #endif
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 76837ab7..328c1c38 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -416,6 +416,9 @@ static const struct gpu_ops gm20b_ops = {
                 .update_runlist = gk20a_fifo_update_runlist,
                 .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault,
                 .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info,
+                .get_mmu_fault_desc = gk20a_fifo_get_mmu_fault_desc,
+                .get_mmu_fault_client_desc = gk20a_fifo_get_mmu_fault_client_desc,
+                .get_mmu_fault_gpc_desc = gm20b_fifo_get_mmu_fault_gpc_desc,
                 .wait_engine_idle = gk20a_fifo_wait_engine_idle,
                 .get_num_fifos = gm20b_fifo_get_num_fifos,
                 .get_pbdma_signature = gk20a_fifo_get_pbdma_signature,