diff options
author | Philip Elcan <pelcan@nvidia.com> | 2018-08-23 14:45:19 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-08-29 20:47:25 -0400 |
commit | 2d0149c9abd74fd6bb59e076cfd46f49097e5662 (patch) | |
tree | 3d14929f7721440b777abfc150a35abbb1b03f36 /drivers/gpu/nvgpu/gm20b/regops_gm20b.c | |
parent | 74639b444251d7adc222400625eb59a3d53d0c0a (diff) |
gpu: nvgpu: resolve MISRA 10.3 violations
MISRA rule 10.3 prohibits implicit assigning of u64 to u32. The nvgpu was
assigning the value returned by ARRAY_SIZE which is a u64 to a u32. This
value was then returned in a function defined by gpu_ops.
This patch changes the return type for these gpu_ops to u64 and updates
the functions that implement the functions and lastly the saved value. This
removes the violation in this instance.
JIRA NVGPU-647
Change-Id: I2b93929633cf4809d8f65ee41f739f45d4c2cda7
Signed-off-by: Philip Elcan <pelcan@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1805588
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/regops_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/regops_gm20b.c | 26 |
1 files changed, 13 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c index aaa055b6..e23a0a62 100644 --- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * Tegra GK20A GPU Debugger Driver Register Ops | 2 | * Tegra GK20A GPU Debugger Driver Register Ops |
3 | * | 3 | * |
4 | * Copyright (c) 2013-2017, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2013-2018, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -261,7 +261,7 @@ static const struct regop_offset_range gm20b_global_whitelist_ranges[] = { | |||
261 | { 0x00504eb0, 1 }, | 261 | { 0x00504eb0, 1 }, |
262 | { 0x00504ef0, 28 }, | 262 | { 0x00504ef0, 28 }, |
263 | }; | 263 | }; |
264 | static const u32 gm20b_global_whitelist_ranges_count = | 264 | static const u64 gm20b_global_whitelist_ranges_count = |
265 | ARRAY_SIZE(gm20b_global_whitelist_ranges); | 265 | ARRAY_SIZE(gm20b_global_whitelist_ranges); |
266 | 266 | ||
267 | /* context */ | 267 | /* context */ |
@@ -351,7 +351,7 @@ static const struct regop_offset_range gm20b_context_whitelist_ranges[] = { | |||
351 | { 0x00504ee8, 1 }, | 351 | { 0x00504ee8, 1 }, |
352 | { 0x00504ef0, 28 }, | 352 | { 0x00504ef0, 28 }, |
353 | }; | 353 | }; |
354 | static const u32 gm20b_context_whitelist_ranges_count = | 354 | static const u64 gm20b_context_whitelist_ranges_count = |
355 | ARRAY_SIZE(gm20b_context_whitelist_ranges); | 355 | ARRAY_SIZE(gm20b_context_whitelist_ranges); |
356 | 356 | ||
357 | /* runcontrol */ | 357 | /* runcontrol */ |
@@ -363,7 +363,7 @@ static const u32 gm20b_runcontrol_whitelist[] = { | |||
363 | 0x00504610, | 363 | 0x00504610, |
364 | 0x00504e10, | 364 | 0x00504e10, |
365 | }; | 365 | }; |
366 | static const u32 gm20b_runcontrol_whitelist_count = | 366 | static const u64 gm20b_runcontrol_whitelist_count = |
367 | ARRAY_SIZE(gm20b_runcontrol_whitelist); | 367 | ARRAY_SIZE(gm20b_runcontrol_whitelist); |
368 | 368 | ||
369 | static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = { | 369 | static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = { |
@@ -374,19 +374,19 @@ static const struct regop_offset_range gm20b_runcontrol_whitelist_ranges[] = { | |||
374 | { 0x00504610, 1 }, | 374 | { 0x00504610, 1 }, |
375 | { 0x00504e10, 1 }, | 375 | { 0x00504e10, 1 }, |
376 | }; | 376 | }; |
377 | static const u32 gm20b_runcontrol_whitelist_ranges_count = | 377 | static const u64 gm20b_runcontrol_whitelist_ranges_count = |
378 | ARRAY_SIZE(gm20b_runcontrol_whitelist_ranges); | 378 | ARRAY_SIZE(gm20b_runcontrol_whitelist_ranges); |
379 | 379 | ||
380 | 380 | ||
381 | /* quad ctl */ | 381 | /* quad ctl */ |
382 | static const u32 gm20b_qctl_whitelist[] = { | 382 | static const u32 gm20b_qctl_whitelist[] = { |
383 | }; | 383 | }; |
384 | static const u32 gm20b_qctl_whitelist_count = | 384 | static const u64 gm20b_qctl_whitelist_count = |
385 | ARRAY_SIZE(gm20b_qctl_whitelist); | 385 | ARRAY_SIZE(gm20b_qctl_whitelist); |
386 | 386 | ||
387 | static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = { | 387 | static const struct regop_offset_range gm20b_qctl_whitelist_ranges[] = { |
388 | }; | 388 | }; |
389 | static const u32 gm20b_qctl_whitelist_ranges_count = | 389 | static const u64 gm20b_qctl_whitelist_ranges_count = |
390 | ARRAY_SIZE(gm20b_qctl_whitelist_ranges); | 390 | ARRAY_SIZE(gm20b_qctl_whitelist_ranges); |
391 | 391 | ||
392 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) | 392 | const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) |
@@ -394,7 +394,7 @@ const struct regop_offset_range *gm20b_get_global_whitelist_ranges(void) | |||
394 | return gm20b_global_whitelist_ranges; | 394 | return gm20b_global_whitelist_ranges; |
395 | } | 395 | } |
396 | 396 | ||
397 | int gm20b_get_global_whitelist_ranges_count(void) | 397 | u64 gm20b_get_global_whitelist_ranges_count(void) |
398 | { | 398 | { |
399 | return gm20b_global_whitelist_ranges_count; | 399 | return gm20b_global_whitelist_ranges_count; |
400 | } | 400 | } |
@@ -404,7 +404,7 @@ const struct regop_offset_range *gm20b_get_context_whitelist_ranges(void) | |||
404 | return gm20b_context_whitelist_ranges; | 404 | return gm20b_context_whitelist_ranges; |
405 | } | 405 | } |
406 | 406 | ||
407 | int gm20b_get_context_whitelist_ranges_count(void) | 407 | u64 gm20b_get_context_whitelist_ranges_count(void) |
408 | { | 408 | { |
409 | return gm20b_context_whitelist_ranges_count; | 409 | return gm20b_context_whitelist_ranges_count; |
410 | } | 410 | } |
@@ -414,7 +414,7 @@ const u32 *gm20b_get_runcontrol_whitelist(void) | |||
414 | return gm20b_runcontrol_whitelist; | 414 | return gm20b_runcontrol_whitelist; |
415 | } | 415 | } |
416 | 416 | ||
417 | int gm20b_get_runcontrol_whitelist_count(void) | 417 | u64 gm20b_get_runcontrol_whitelist_count(void) |
418 | { | 418 | { |
419 | return gm20b_runcontrol_whitelist_count; | 419 | return gm20b_runcontrol_whitelist_count; |
420 | } | 420 | } |
@@ -424,7 +424,7 @@ const struct regop_offset_range *gm20b_get_runcontrol_whitelist_ranges(void) | |||
424 | return gm20b_runcontrol_whitelist_ranges; | 424 | return gm20b_runcontrol_whitelist_ranges; |
425 | } | 425 | } |
426 | 426 | ||
427 | int gm20b_get_runcontrol_whitelist_ranges_count(void) | 427 | u64 gm20b_get_runcontrol_whitelist_ranges_count(void) |
428 | { | 428 | { |
429 | return gm20b_runcontrol_whitelist_ranges_count; | 429 | return gm20b_runcontrol_whitelist_ranges_count; |
430 | } | 430 | } |
@@ -434,7 +434,7 @@ const u32 *gm20b_get_qctl_whitelist(void) | |||
434 | return gm20b_qctl_whitelist; | 434 | return gm20b_qctl_whitelist; |
435 | } | 435 | } |
436 | 436 | ||
437 | int gm20b_get_qctl_whitelist_count(void) | 437 | u64 gm20b_get_qctl_whitelist_count(void) |
438 | { | 438 | { |
439 | return gm20b_qctl_whitelist_count; | 439 | return gm20b_qctl_whitelist_count; |
440 | } | 440 | } |
@@ -444,7 +444,7 @@ const struct regop_offset_range *gm20b_get_qctl_whitelist_ranges(void) | |||
444 | return gm20b_qctl_whitelist_ranges; | 444 | return gm20b_qctl_whitelist_ranges; |
445 | } | 445 | } |
446 | 446 | ||
447 | int gm20b_get_qctl_whitelist_ranges_count(void) | 447 | u64 gm20b_get_qctl_whitelist_ranges_count(void) |
448 | { | 448 | { |
449 | return gm20b_qctl_whitelist_ranges_count; | 449 | return gm20b_qctl_whitelist_ranges_count; |
450 | } | 450 | } |