gpu: nvgpu: add corresponding whitelists for per-context registers.

For gp10b, there is a single whitelist maintained for both global and
per-context registers, for gm20b, there are separate whitelists
maintained for global and per-context registers. This patch updates
the failing registers in the bug into the per-context list.

Bug 200363092

Change-Id: I1906ea46d4b37f9aa8d13833a5bba4a5f7c6bbe5
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1603660
(cherry picked from commit 1ec466151066eff40ca96ed41c8166602a7711ed)
Reviewed-on: https://git-master.nvidia.com/r/1688274
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
index 79c980f4..aaa055b6 100644
--- a/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/regops_gm20b.c
@@ -269,7 +269,12 @@ static const u32 gm20b_global_whitelist_ranges_count =
 static const struct regop_offset_range gm20b_context_whitelist_ranges[] = {
         { 0x0000259c,   1 },
         { 0x0000280c,   1 },
+        { 0x00140028,   1 },
+        { 0x00180040,  52 },
+        { 0x001a0040,  52 },
+        { 0x001b0040,  52 },
         { 0x00400500,   1 },
+        { 0x0040415c,   1 },
         { 0x00405b40,   1 },
         { 0x00418e00,   1 },
         { 0x00418e34,   1 },
@@ -324,6 +329,7 @@ static const struct regop_offset_range gm20b_context_whitelist_ranges[] = {
         { 0x00503ee8,   2 },
         { 0x00504490,   1 },
         { 0x00504508,   2 },
+        { 0x00504600,   4 },
         { 0x00504604,   3 },
         { 0x00504614,   6 },
         { 0x00504634,   2 },