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authorMahantesh Kumbar <mkumbar@nvidia.com>2017-07-04 01:55:00 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-07-05 03:39:21 -0400
commite808d345f11885453fc65862ec4e3dd4a375ff6d (patch)
treeccc3bb1ade5ff991ca1805084b76f154ca9736ee /drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
parent2cf964d175abc0f3eae9ed0e01e6eeed5cd6b4da (diff)
gpu: nvgpu: rename gk20a_pmu_cmd_post()
- rename gk20a_pmu_cmd_post() to nvgpu_pmu_cmd_post() - replaced gk20a_pmu_cmd_post() with nvgpu_pmu_cmd_post() wherever called. JIRA NVGPU-93 Change-Id: I7ca43170646bab1657a4b4cf125d9f94d589b0eb Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com> Reviewed-on: https://git-master/r/1512904 Reviewed-by: Automatic_Commit_Validation_User GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/pmu_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/pmu_gm20b.c4
1 files changed, 2 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 3b655b62..ee55c8ef 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -153,7 +153,7 @@ int gm20b_pmu_init_acr(struct gk20a *g)
153 cmd.cmd.acr.init_wpr.regionid = 0x01; 153 cmd.cmd.acr.init_wpr.regionid = 0x01;
154 cmd.cmd.acr.init_wpr.wproffset = 0x00; 154 cmd.cmd.acr.init_wpr.wproffset = 0x00;
155 gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION"); 155 gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION");
156 gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, 156 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
157 pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0); 157 pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0);
158 158
159 gk20a_dbg_fn("done"); 159 gk20a_dbg_fn("done");
@@ -217,7 +217,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags)
217 cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id; 217 cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id;
218 gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n", 218 gm20b_dbg_pmu("cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n",
219 falcon_id); 219 falcon_id);
220 gk20a_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ, 220 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
221 pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0); 221 pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);
222 } 222 }
223 223