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authorSupriya <ssharatkumar@nvidia.com>2016-03-21 08:09:48 -0400
committerTerje Bergstrom <tbergstrom@nvidia.com>2016-04-06 22:38:19 -0400
commitbf82cd220a1ea4f8e327bc9bae51e36669c43778 (patch)
tree6f44623e05efc4aab7654fb106dc3b82472863f6 /drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
parent135d6db448cfaf5a366e6572f1a02a67e35d70db (diff)
gpu: nvgpu: Add Fuse prints on PMU Halt
-Print fuse values in case of PMU halt error -and mailbox reads 0xDEADDEAD Bug 1737044 Change-Id: I59f5fcf4a69bdd2a2eea81a69dd99bb9c4c21e1d Signed-off-by: Supriya <ssharatkumar@nvidia.com> Reviewed-on: http://git-master/r/1113464 (cherry picked from commit d0320eed72c5070c4fcc7564c02fa38599984751) Reviewed-on: http://git-master/r/1120429 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/pmu_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/pmu_gm20b.c14
1 files changed, 14 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index ce3da2b6..34d1c30c 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -14,12 +14,14 @@
14 */ 14 */
15 15
16#include <linux/delay.h> /* for udelay */ 16#include <linux/delay.h> /* for udelay */
17#include <linux/tegra-fuse.h>
17#include "gk20a/gk20a.h" 18#include "gk20a/gk20a.h"
18#include "gk20a/pmu_gk20a.h" 19#include "gk20a/pmu_gk20a.h"
19#include "acr_gm20b.h" 20#include "acr_gm20b.h"
20#include "pmu_gm20b.h" 21#include "pmu_gm20b.h"
21#include "hw_gr_gm20b.h" 22#include "hw_gr_gm20b.h"
22#include "hw_pwr_gm20b.h" 23#include "hw_pwr_gm20b.h"
24#include "hw_fuse_gm20b.h"
23 25
24/*! 26/*!
25 * Structure/object which single register write need to be done during PG init 27 * Structure/object which single register write need to be done during PG init
@@ -289,6 +291,17 @@ static void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr)
289 gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr); 291 gk20a_writel(g, pwr_falcon_dmatrfbase_r(), addr);
290} 292}
291 293
294/*Dump Security related fuses*/
295static void pmu_dump_security_fuses_gm20b(struct gk20a *g)
296{
297 gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x",
298 gk20a_readl(g, fuse_opt_sec_debug_en_r()));
299 gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
300 gk20a_readl(g, fuse_opt_priv_sec_en_r()));
301 gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
302 tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0));
303}
304
292void gm20b_init_pmu_ops(struct gpu_ops *gops) 305void gm20b_init_pmu_ops(struct gpu_ops *gops)
293{ 306{
294 if (gops->privsecurity) { 307 if (gops->privsecurity) {
@@ -309,4 +322,5 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops)
309 gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; 322 gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics;
310 gops->pmu.pmu_pg_grinit_param = NULL; 323 gops->pmu.pmu_pg_grinit_param = NULL;
311 gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL; 324 gops->pmu.send_lrf_tex_ltc_dram_overide_en_dis_cmd = NULL;
325 gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b;
312} 326}