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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-04-06 14:01:46 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-04-07 16:48:18 -0400
commitbb72b7e2ed215b26e1d9b94534c24ab4cfa52801 (patch)
tree2a8e781838616f4640d7ef3e5c04ae7d996e0ecf /drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
parent85f27cec5d010d4ac0f4646f11f145d4b3a122e4 (diff)
gpu: nvgpu: gm20b: Use new error macros
gk20a_err() and gk20a_warn() require a struct device pointer, which is not portable across operating systems. The new nvgpu_err() and nvgpu_warn() macros take struct gk20a pointer. Convert code to use the more portable macros. JIRA NVGPU-16 Change-Id: Ic27fb98e03a982e5a1cf672cb4e8f87ecea10a5b Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1457345 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/pmu_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/pmu_gm20b.c9
1 files changed, 4 insertions, 5 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 38509f69..730c5eaf 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -242,8 +242,7 @@ static int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
242 &g->ops.pmu.lspmuwprinitdone, 1); 242 &g->ops.pmu.lspmuwprinitdone, 1);
243 /* check again if it still not ready indicate an error */ 243 /* check again if it still not ready indicate an error */
244 if (!g->ops.pmu.lspmuwprinitdone) { 244 if (!g->ops.pmu.lspmuwprinitdone) {
245 gk20a_err(dev_from_gk20a(g), 245 nvgpu_err(g, "PMU not ready to load LSF");
246 "PMU not ready to load LSF");
247 return -ETIMEDOUT; 246 return -ETIMEDOUT;
248 } 247 }
249 } 248 }
@@ -266,12 +265,12 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g)
266{ 265{
267 u32 val; 266 u32 val;
268 267
269 gk20a_err(dev_from_gk20a(g), "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x", 268 nvgpu_err(g, "FUSE_OPT_SEC_DEBUG_EN_0 : 0x%x",
270 gk20a_readl(g, fuse_opt_sec_debug_en_r())); 269 gk20a_readl(g, fuse_opt_sec_debug_en_r()));
271 gk20a_err(dev_from_gk20a(g), "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x", 270 nvgpu_err(g, "FUSE_OPT_PRIV_SEC_EN_0 : 0x%x",
272 gk20a_readl(g, fuse_opt_priv_sec_en_r())); 271 gk20a_readl(g, fuse_opt_priv_sec_en_r()));
273 tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val); 272 tegra_fuse_readl(FUSE_GCPLEX_CONFIG_FUSE_0, &val);
274 gk20a_err(dev_from_gk20a(g), "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x", 273 nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0 : 0x%x",
275 val); 274 val);
276} 275}
277 276