nvgpu: pmu: Use ops to get PMU queue HEAD/TAIL.

pmu_queue_head() & pmu_queue_tail() are updated
to use gops to include chip specific PMU queue
head/tail registers.

JIRA GV11B-30

Change-Id: I9c3d6a4601ba2767f9ada95642052044e2b79747
Signed-off-by: Deepak Goyal <dgoyal@nvidia.com>
Reviewed-on: http://git-master/r/1283266
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 4 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 4b87b877..3c09600d 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -289,6 +289,10 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops)
                 gops->pmu.init_wpr_region = NULL;
         }
         gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg;
+        gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r;
+        gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v;
+        gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r;
+        gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v;
         gops->pmu.lspmuwprinitdone = 0;
         gops->pmu.fecsbootstrapdone = false;
         gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase;