diff options
author | Alex Waterman <alexw@nvidia.com> | 2016-12-19 18:23:01 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-01-18 19:46:38 -0500 |
commit | 8e53d790902b8a40098a5851584ae7ba58b357b6 (patch) | |
tree | 48fd2c6b26ac3137dd2dfe5255cc04f24bcc8834 /drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |
parent | 6e2237ef622113b8fa1149aa48988a99fa30594f (diff) |
gpu: nvgpu: Use timer API in gm20b code
Use the timer API instead of Linux specific APIs for handling
timeouts.
Also, lower the L2 timeout from 1 second (absurdly long) to 5ms.
Bug 1799159
Change-Id: I27dbc35b12e9bc22ff2207bb87543f76203e20f1
Signed-off-by: Alex Waterman <alexw@nvidia.com>
Reviewed-on: http://git-master/r/1273825
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/pmu_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 13 |
1 files changed, 9 insertions, 4 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 2e568e83..4b87b877 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -22,6 +22,8 @@ | |||
22 | #include "acr_gm20b.h" | 22 | #include "acr_gm20b.h" |
23 | #include "pmu_gm20b.h" | 23 | #include "pmu_gm20b.h" |
24 | 24 | ||
25 | #include <nvgpu/timers.h> | ||
26 | |||
25 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> | 27 | #include <nvgpu/hw/gm20b/hw_gr_gm20b.h> |
26 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> | 28 | #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h> |
27 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | 29 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> |
@@ -173,21 +175,24 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg, | |||
173 | gk20a_dbg_fn("done"); | 175 | gk20a_dbg_fn("done"); |
174 | } | 176 | } |
175 | 177 | ||
176 | static int pmu_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout, u32 val) | 178 | static int pmu_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout_ms, |
179 | u32 val) | ||
177 | { | 180 | { |
178 | unsigned long end_jiffies = jiffies + msecs_to_jiffies(timeout); | ||
179 | unsigned long delay = GR_FECS_POLL_INTERVAL; | 181 | unsigned long delay = GR_FECS_POLL_INTERVAL; |
180 | u32 reg; | 182 | u32 reg; |
183 | struct nvgpu_timeout timeout; | ||
181 | 184 | ||
182 | gk20a_dbg_fn(""); | 185 | gk20a_dbg_fn(""); |
183 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); | 186 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); |
187 | |||
188 | nvgpu_timeout_init(g, &timeout, (int)timeout_ms, NVGPU_TIMER_CPU_TIMER); | ||
189 | |||
184 | do { | 190 | do { |
185 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); | 191 | reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); |
186 | if (reg == val) | 192 | if (reg == val) |
187 | return 0; | 193 | return 0; |
188 | udelay(delay); | 194 | udelay(delay); |
189 | } while (time_before(jiffies, end_jiffies) || | 195 | } while (!nvgpu_timeout_expired(&timeout)); |
190 | !tegra_platform_is_silicon()); | ||
191 | 196 | ||
192 | return -ETIMEDOUT; | 197 | return -ETIMEDOUT; |
193 | } | 198 | } |