diff options
author | Mahantesh Kumbar <mkumbar@nvidia.com> | 2018-09-10 11:41:49 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2018-09-24 11:12:03 -0400 |
commit | 863b47064445b3dd5cdc354821c8d3d14deade33 (patch) | |
tree | 1e53f26c1549d1970d752f74ab82a4d55642620b /drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |
parent | fdf77eda18b59c305d4dd8436d8b09d42ec4718a (diff) |
gpu: nvgpu: PMU init sequence change
-Moved PMU RTOS init & start RTOS from acr_gm20b.c file pmu.c
method nvgpu_init_pmu_support()
-Modified nvgpu_init_pmu_support() to init required interface
for PMU RTOS & does start PMU RTOS in secure & non-secure
based on NVGPU_SEC_PRIVSECURITY flag.
-Created secured_pmu_start ops under PMU ops to start PMU
falcon in low secure mode.
-Updated PMU ops update_lspmu_cmdline_args, setup_apertures &
secured_pmu_start assignment for gp106 & gv100 to support
modified PMU init sequence.
-Removed duplicate PMU non-secure bootstrap code from multiple
files & defined gm20b_ns_pmu_setup_hw_and_bootstrap()method
to handle non secure PMU bootstrap, reused this method
for need chips.
JIRA NVGPU-1146
Change-Id: I3957da2936b3c4ea0c985e67802c847c38de7c89
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1818099
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/pmu_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 72 |
1 files changed, 72 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index 6e764ac5..df0ae58d 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -278,6 +278,72 @@ bool gm20b_pmu_is_debug_mode_en(struct gk20a *g) | |||
278 | return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U; | 278 | return pwr_pmu_scpctl_stat_debug_mode_v(ctl_stat) != 0U; |
279 | } | 279 | } |
280 | 280 | ||
281 | int gm20b_ns_pmu_setup_hw_and_bootstrap(struct gk20a *g) | ||
282 | { | ||
283 | struct nvgpu_pmu *pmu = &g->pmu; | ||
284 | |||
285 | nvgpu_log_fn(g, " "); | ||
286 | |||
287 | nvgpu_mutex_acquire(&pmu->isr_mutex); | ||
288 | nvgpu_flcn_reset(pmu->flcn); | ||
289 | pmu->isr_enabled = true; | ||
290 | nvgpu_mutex_release(&pmu->isr_mutex); | ||
291 | |||
292 | /* setup apertures - virtual */ | ||
293 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
294 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
295 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
296 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
297 | /* setup apertures - physical */ | ||
298 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
299 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
300 | pwr_fbif_transcfg_target_local_fb_f()); | ||
301 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
302 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
303 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
304 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
305 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
306 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
307 | |||
308 | return g->ops.pmu.pmu_nsbootstrap(pmu); | ||
309 | } | ||
310 | |||
311 | void gm20b_pmu_setup_apertures(struct gk20a *g) | ||
312 | { | ||
313 | /* setup apertures - virtual */ | ||
314 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_UCODE), | ||
315 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
316 | pwr_fbif_transcfg_target_local_fb_f()); | ||
317 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_VIRT), | ||
318 | pwr_fbif_transcfg_mem_type_virtual_f()); | ||
319 | /* setup apertures - physical */ | ||
320 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_VID), | ||
321 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
322 | pwr_fbif_transcfg_target_local_fb_f()); | ||
323 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_COH), | ||
324 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
325 | pwr_fbif_transcfg_target_coherent_sysmem_f()); | ||
326 | gk20a_writel(g, pwr_fbif_transcfg_r(GK20A_PMU_DMAIDX_PHYS_SYS_NCOH), | ||
327 | pwr_fbif_transcfg_mem_type_physical_f() | | ||
328 | pwr_fbif_transcfg_target_noncoherent_sysmem_f()); | ||
329 | } | ||
330 | |||
331 | void gm20b_update_lspmu_cmdline_args(struct gk20a *g) | ||
332 | { | ||
333 | struct nvgpu_pmu *pmu = &g->pmu; | ||
334 | /*Copying pmu cmdline args*/ | ||
335 | g->ops.pmu_ver.set_pmu_cmdline_args_cpu_freq(pmu, | ||
336 | g->ops.clk.get_rate(g, CTRL_CLK_DOMAIN_PWRCLK)); | ||
337 | g->ops.pmu_ver.set_pmu_cmdline_args_secure_mode(pmu, 1); | ||
338 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_size( | ||
339 | pmu, GK20A_PMU_TRACE_BUFSIZE); | ||
340 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_base(pmu); | ||
341 | g->ops.pmu_ver.set_pmu_cmdline_args_trace_dma_idx( | ||
342 | pmu, GK20A_PMU_DMAIDX_VIRT); | ||
343 | nvgpu_flcn_copy_to_dmem(pmu->flcn, g->acr.pmu_args, | ||
344 | (u8 *)(g->ops.pmu_ver.get_pmu_cmdline_args_ptr(pmu)), | ||
345 | g->ops.pmu_ver.get_pmu_cmdline_args_size(pmu), 0); | ||
346 | } | ||
281 | 347 | ||
282 | static int gm20b_bl_bootstrap(struct gk20a *g, | 348 | static int gm20b_bl_bootstrap(struct gk20a *g, |
283 | struct nvgpu_falcon_bl_info *bl_info) | 349 | struct nvgpu_falcon_bl_info *bl_info) |
@@ -337,3 +403,9 @@ int gm20b_pmu_setup_hw_and_bl_bootstrap(struct gk20a *g, | |||
337 | exit: | 403 | exit: |
338 | return err; | 404 | return err; |
339 | } | 405 | } |
406 | |||
407 | void gm20b_secured_pmu_start(struct gk20a *g) | ||
408 | { | ||
409 | gk20a_writel(g, pwr_falcon_cpuctl_alias_r(), | ||
410 | pwr_falcon_cpuctl_startcpu_f(1)); | ||
411 | } | ||