gpu: nvgpu: invoke calls to methods in pmu_gk20a.h via HAL

In nvgpu repository, we have multiple accesses to methods in
pmu_gk20a.h which have register accesses. Instead of directly invoking
these methods, these are now called via HALs. Some common methods such
as pmu_wait_message_cond which donot have any register accesses
are moved to pmu_ipc.c and the method declarations are moved
to pmu.h. Also, changed gm20b_pmu_dbg to
nvgpu_dbg_pmu all across the code base. This would remove all
indirect dependencies via gk20a.h into pmu_gk20a.h. As a result
pmu_gk20a.h is now removed from gk20a.h

JIRA-597

Change-Id: Id54b2684ca39362fda7626238c3116cd49e92080
Signed-off-by: Debarshi Dutta <ddutta@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1804283
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 6 insertions, 10 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 286a1979..38970f73 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -37,10 +37,6 @@
 #include <nvgpu/hw/gm20b/hw_gr_gm20b.h>
 #include <nvgpu/hw/gm20b/hw_pwr_gm20b.h>
 
-#define gm20b_dbg_pmu(g, fmt, arg...) \
-        nvgpu_log(g, gpu_dbg_pmu, fmt, ##arg)
-
-
 /* PROD settings for ELPG sequencing registers*/
 static struct pg_init_sequence_list _pginitseq_gm20b[] = {
                 { 0x0010ab10, 0x8180},
@@ -129,7 +125,7 @@ static void pmu_handle_acr_init_wpr_msg(struct gk20a *g, struct pmu_msg *msg,
 {
         nvgpu_log_fn(g, " ");
 
-        gm20b_dbg_pmu(g, "reply PMU_ACR_CMD_ID_INIT_WPR_REGION");
+        nvgpu_pmu_dbg(g, "reply PMU_ACR_CMD_ID_INIT_WPR_REGION");
 
         if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) {
                 g->pmu_lsf_pmu_wpr_init_done = 1;
@@ -154,7 +150,7 @@ int gm20b_pmu_init_acr(struct gk20a *g)
         cmd.cmd.acr.init_wpr.cmd_type = PMU_ACR_CMD_ID_INIT_WPR_REGION;
         cmd.cmd.acr.init_wpr.regionid = 0x01;
         cmd.cmd.acr.init_wpr.wproffset = 0x00;
-        gm20b_dbg_pmu(g, "cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION");
+        nvgpu_pmu_dbg(g, "cmd post PMU_ACR_CMD_ID_INIT_WPR_REGION");
         nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                         pmu_handle_acr_init_wpr_msg, pmu, &seq, ~0);
 
@@ -169,9 +165,9 @@ void pmu_handle_fecs_boot_acr_msg(struct gk20a *g, struct pmu_msg *msg,
         nvgpu_log_fn(g, " ");
 
 
-        gm20b_dbg_pmu(g, "reply PMU_ACR_CMD_ID_BOOTSTRAP_FALCON");
+        nvgpu_pmu_dbg(g, "reply PMU_ACR_CMD_ID_BOOTSTRAP_FALCON");
 
-        gm20b_dbg_pmu(g, "response code = %x\n", msg->msg.acr.acrmsg.falconid);
+        nvgpu_pmu_dbg(g, "response code = %x\n", msg->msg.acr.acrmsg.falconid);
         g->pmu_lsf_loaded_falcon_id = msg->msg.acr.acrmsg.falconid;
         nvgpu_log_fn(g, "done");
 }
@@ -207,7 +203,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags)
 
         nvgpu_log_fn(g, " ");
 
-        gm20b_dbg_pmu(g, "wprinit status = %x\n", g->pmu_lsf_pmu_wpr_init_done);
+        nvgpu_pmu_dbg(g, "wprinit status = %x\n", g->pmu_lsf_pmu_wpr_init_done);
         if (g->pmu_lsf_pmu_wpr_init_done) {
                 /* send message to load FECS falcon */
                 memset(&cmd, 0, sizeof(struct pmu_cmd));
@@ -218,7 +214,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags)
                   PMU_ACR_CMD_ID_BOOTSTRAP_FALCON;
                 cmd.cmd.acr.bootstrap_falcon.flags = flags;
                 cmd.cmd.acr.bootstrap_falcon.falconid = falcon_id;
-                gm20b_dbg_pmu(g, "cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n",
+                nvgpu_pmu_dbg(g, "cmd post PMU_ACR_CMD_ID_BOOTSTRAP_FALCON: %x\n",
                                 falcon_id);
                 nvgpu_pmu_cmd_post(g, &cmd, NULL, NULL, PMU_COMMAND_QUEUE_HPQ,
                                 pmu_handle_fecs_boot_acr_msg, pmu, &seq, ~0);