diff options
author | Sunny He <suhe@nvidia.com> | 2017-08-01 20:10:42 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-08-21 16:06:07 -0400 |
commit | 5f010177de985c901c33c914efe70a8498a5974f (patch) | |
tree | 1b1a2ac1ab71608a0754a7eb64222f5d198e793c /drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |
parent | b50b379c192714d0d08c3f2d33e90c95cf795253 (diff) |
gpu: nvgpu: Reorg pmu HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the
pmu sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I8839ac99e87153637005e23b3013237f57275c54
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1530982
Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com>
Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com>
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/pmu_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | 48 |
1 files changed, 3 insertions, 45 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c index a5940fcf..99241a53 100644 --- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c | |||
@@ -102,7 +102,7 @@ static struct pg_init_sequence_list _pginitseq_gm20b[] = { | |||
102 | { 0x0010e040, 0x00000000}, | 102 | { 0x0010e040, 0x00000000}, |
103 | }; | 103 | }; |
104 | 104 | ||
105 | static int gm20b_pmu_setup_elpg(struct gk20a *g) | 105 | int gm20b_pmu_setup_elpg(struct gk20a *g) |
106 | { | 106 | { |
107 | int ret = 0; | 107 | int ret = 0; |
108 | u32 reg_writes; | 108 | u32 reg_writes; |
@@ -226,7 +226,7 @@ void gm20b_pmu_load_lsf(struct gk20a *g, u32 falcon_id, u32 flags) | |||
226 | return; | 226 | return; |
227 | } | 227 | } |
228 | 228 | ||
229 | static int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) | 229 | int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask) |
230 | { | 230 | { |
231 | u32 err = 0; | 231 | u32 err = 0; |
232 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; | 232 | u32 flags = PMU_ACR_CMD_BOOTSTRAP_FALCON_FLAGS_RESET_YES; |
@@ -261,7 +261,7 @@ void gm20b_write_dmatrfbase(struct gk20a *g, u32 addr) | |||
261 | } | 261 | } |
262 | 262 | ||
263 | /*Dump Security related fuses*/ | 263 | /*Dump Security related fuses*/ |
264 | static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | 264 | void pmu_dump_security_fuses_gm20b(struct gk20a *g) |
265 | { | 265 | { |
266 | u32 val; | 266 | u32 val; |
267 | 267 | ||
@@ -272,45 +272,3 @@ static void pmu_dump_security_fuses_gm20b(struct gk20a *g) | |||
272 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); | 272 | nvgpu_tegra_fuse_read_gcplex_config_fuse(g, &val); |
273 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); | 273 | nvgpu_err(g, "FUSE_GCPLEX_CONFIG_FUSE_0: 0x%x", val); |
274 | } | 274 | } |
275 | |||
276 | void gm20b_init_pmu_ops(struct gk20a *g) | ||
277 | { | ||
278 | struct gpu_ops *gops = &g->ops; | ||
279 | |||
280 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | ||
281 | gm20b_init_secure_pmu(gops); | ||
282 | gops->pmu.init_wpr_region = gm20b_pmu_init_acr; | ||
283 | gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; | ||
284 | } else { | ||
285 | gk20a_init_pmu_ops(gops); | ||
286 | gops->pmu.pmu_setup_hw_and_bootstrap = | ||
287 | gm20b_init_nspmu_setup_hw1; | ||
288 | gops->pmu.load_lsfalcon_ucode = NULL; | ||
289 | gops->pmu.init_wpr_region = NULL; | ||
290 | } | ||
291 | gops->pmu.pmu_setup_elpg = gm20b_pmu_setup_elpg; | ||
292 | gops->pmu.pmu_get_queue_head = pwr_pmu_queue_head_r; | ||
293 | gops->pmu.pmu_get_queue_head_size = pwr_pmu_queue_head__size_1_v; | ||
294 | gops->pmu.pmu_get_queue_tail = pwr_pmu_queue_tail_r; | ||
295 | gops->pmu.pmu_get_queue_tail_size = pwr_pmu_queue_tail__size_1_v; | ||
296 | gops->pmu.pmu_queue_head = gk20a_pmu_queue_head; | ||
297 | gops->pmu.pmu_queue_tail = gk20a_pmu_queue_tail; | ||
298 | gops->pmu.pmu_msgq_tail = gk20a_pmu_msgq_tail; | ||
299 | gops->pmu.pmu_mutex_size = pwr_pmu_mutex__size_1_v; | ||
300 | gops->pmu.pmu_mutex_acquire = gk20a_pmu_mutex_acquire; | ||
301 | gops->pmu.pmu_mutex_release = gk20a_pmu_mutex_release; | ||
302 | g->pmu_lsf_pmu_wpr_init_done = 0; | ||
303 | __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); | ||
304 | gops->pmu.write_dmatrfbase = gm20b_write_dmatrfbase; | ||
305 | gops->pmu.pmu_elpg_statistics = gk20a_pmu_elpg_statistics; | ||
306 | gops->pmu.pmu_pg_init_param = NULL; | ||
307 | gops->pmu.pmu_pg_supported_engines_list = gk20a_pmu_pg_engines_list; | ||
308 | gops->pmu.pmu_pg_engines_feature_list = gk20a_pmu_pg_feature_list; | ||
309 | gops->pmu.pmu_is_lpwr_feature_supported = NULL; | ||
310 | gops->pmu.pmu_lpwr_enable_pg = NULL; | ||
311 | gops->pmu.pmu_lpwr_disable_pg = NULL; | ||
312 | gops->pmu.pmu_pg_param_post_init = NULL; | ||
313 | gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b; | ||
314 | gops->pmu.reset_engine = gk20a_pmu_engine_reset; | ||
315 | gops->pmu.is_engine_in_reset = gk20a_pmu_is_engine_in_reset; | ||
316 | } | ||