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authorSrirangan <smadhavan@nvidia.com>2018-08-23 02:37:41 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-08-28 09:47:28 -0400
commit4032e8915a65aa94f8b556676c5606683ec28f52 (patch)
treedc16ddcc61f9fed52c1c687bb02e6ec13edd28c6 /drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
parent8676b2e65b786497c4a0609f06143e7d1bb1a3c0 (diff)
gpu: nvgpu: gm20b: Fix MISRA 15.6 violations
MISRA Rule-15.6 requires that all if-else blocks be enclosed in braces, including single statement blocks. Fix errors due to single statement if blocks without braces, introducing the braces. JIRA NVGPU-671 Change-Id: I1651ae8ee680bdeb48606569c4e8c2fc7cb87f20 Signed-off-by: Srirangan <smadhavan@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1805077 Reviewed-by: Konsta Holtta <kholtta@nvidia.com> Reviewed-by: svc-misra-checker <svc-misra-checker@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/pmu_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/pmu_gm20b.c9
1 files changed, 6 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 53bec96f..286a1979 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -131,8 +131,9 @@ static void pmu_handle_acr_init_wpr_msg(struct gk20a *g, struct pmu_msg *msg,
131 131
132 gm20b_dbg_pmu(g, "reply PMU_ACR_CMD_ID_INIT_WPR_REGION"); 132 gm20b_dbg_pmu(g, "reply PMU_ACR_CMD_ID_INIT_WPR_REGION");
133 133
134 if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) 134 if (msg->msg.acr.acrmsg.errorcode == PMU_ACR_SUCCESS) {
135 g->pmu_lsf_pmu_wpr_init_done = 1; 135 g->pmu_lsf_pmu_wpr_init_done = 1;
136 }
136 nvgpu_log_fn(g, "done"); 137 nvgpu_log_fn(g, "done");
137} 138}
138 139
@@ -189,8 +190,9 @@ static int pmu_gm20b_ctx_wait_lsf_ready(struct gk20a *g, u32 timeout_ms,
189 190
190 do { 191 do {
191 reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0)); 192 reg = gk20a_readl(g, gr_fecs_ctxsw_mailbox_r(0));
192 if (reg == val) 193 if (reg == val) {
193 return 0; 194 return 0;
195 }
194 nvgpu_udelay(delay); 196 nvgpu_udelay(delay);
195 } while (!nvgpu_timeout_expired(&timeout)); 197 } while (!nvgpu_timeout_expired(&timeout));
196 198
@@ -233,8 +235,9 @@ int gm20b_load_falcon_ucode(struct gk20a *g, u32 falconidmask)
233 unsigned long timeout = gk20a_get_gr_idle_timeout(g); 235 unsigned long timeout = gk20a_get_gr_idle_timeout(g);
234 236
235 /* GM20B PMU supports loading FECS only */ 237 /* GM20B PMU supports loading FECS only */
236 if (!(falconidmask == (1 << LSF_FALCON_ID_FECS))) 238 if (!(falconidmask == (1 << LSF_FALCON_ID_FECS))) {
237 return -EINVAL; 239 return -EINVAL;
240 }
238 /* check whether pmu is ready to bootstrap lsf if not wait for it */ 241 /* check whether pmu is ready to bootstrap lsf if not wait for it */
239 if (!g->pmu_lsf_pmu_wpr_init_done) { 242 if (!g->pmu_lsf_pmu_wpr_init_done) {
240 pmu_wait_message_cond(&g->pmu, 243 pmu_wait_message_cond(&g->pmu,