gpu: nvgpu: PMU reset reorg

- nvgpu_pmu_reset() as pmu reset for
all chips & removed gk20a_pmu_reset() &
gp106_pmu_reset() along with dependent
code.

- Created ops to do PMU engine reset & to
know the engine reset status

- Removed pmu.reset ops & replaced with
nvgpu_flcn_reset(pmu->flcn)

- Moved sec2 reset to sec2_gp106 from
pmu_gp106 & cleaned PMU code part of sec2.

JIRA NVGPU-99

Change-Id: I7575e4ca2b34922d73d171f6a41bfcdc2f40dc96
Signed-off-by: Mahantesh Kumbar <mkumbar@nvidia.com>
Reviewed-on: https://git-master/r/1507881
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
index 6c5a2502..3b655b62 100644
--- a/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/pmu_gm20b.c
@@ -309,5 +309,6 @@ void gm20b_init_pmu_ops(struct gpu_ops *gops)
         gops->pmu.pmu_lpwr_disable_pg = NULL;
         gops->pmu.pmu_pg_param_post_init = NULL;
         gops->pmu.dump_secure_fuses = pmu_dump_security_fuses_gm20b;
-        gops->pmu.reset = NULL;
+        gops->pmu.reset_engine = gk20a_pmu_engine_reset;
+        gops->pmu.is_engine_in_reset = gk20a_pmu_is_engine_in_reset;
 }