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authorTerje Bergstrom <tbergstrom@nvidia.com>2014-09-10 07:32:08 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:23 -0400
commit78c46b85556ca1cf0fd15d504a309f9c508064e6 (patch)
tree47b5873f2c234aec905b3c0c5d95992b5fcf5e05 /drivers/gpu/nvgpu/gm20b/mm_gm20b.c
parent9981cf44243e644e7ba3f01b66e08bea5b24979b (diff)
gpu: nvgpu: gm20b: Fix build warnings
Fix build warnings by removing the unused variables, functions and duplicated code. Enable -Werror to prevent new build warnings. Change-Id: Ifd73344a6e12497e6dca595ac7a6edd7ca698f88 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/497374 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: Juha Tukkinen <jtukkinen@nvidia.com> Reviewed-by: Deepak Nibade <dnibade@nvidia.com> GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/mm_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/mm_gm20b.c50
1 files changed, 0 insertions, 50 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index afb04cae..278ae9a6 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -90,52 +90,6 @@ fail:
90 90
91} 91}
92 92
93static void allocate_gmmu_pde_sparse(struct vm_gk20a *vm, u32 i)
94{
95 bool small_valid, big_valid;
96 u64 pte_addr[2] = {0, 0};
97 struct page_table_gk20a *small_pte =
98 vm->pdes.ptes[gmmu_page_size_small] + i;
99 struct page_table_gk20a *big_pte =
100 vm->pdes.ptes[gmmu_page_size_big] + i;
101 u32 pde_v[2] = {0, 0};
102 u32 *pde;
103
104 gk20a_dbg_fn("");
105
106 small_valid = small_pte && small_pte->ref;
107 big_valid = big_pte && big_pte->ref;
108
109 if (small_valid)
110 pte_addr[gmmu_page_size_small] =
111 gk20a_mm_iova_addr(small_pte->sgt->sgl);
112 if (big_valid)
113 pte_addr[gmmu_page_size_big] =
114 gk20a_mm_iova_addr(big_pte->sgt->sgl);
115
116 pde_v[0] = gmmu_pde_size_full_f();
117 pde_v[0] |= gmmu_pde_aperture_big_invalid_f();
118 pde_v[1] |= gmmu_pde_aperture_small_invalid_f() |
119 gmmu_pde_vol_big_true_f();
120
121 pde = pde_from_index(vm, i);
122
123 gk20a_mem_wr32(pde, 0, pde_v[0]);
124 gk20a_mem_wr32(pde, 1, pde_v[1]);
125
126 smp_mb();
127
128 FLUSH_CPU_DCACHE(pde,
129 sg_phys(vm->pdes.sgt->sgl) + (i*gmmu_pde__size_v()),
130 sizeof(u32)*2);
131
132 gk20a_mm_l2_invalidate(vm->mm->g);
133
134 gk20a_dbg(gpu_dbg_pte, "pde:%d = 0x%x,0x%08x\n", i, pde_v[1], pde_v[0]);
135
136 vm->tlb_dirty = true;
137}
138
139static bool gm20b_vm_is_pde_in_range(struct vm_gk20a *vm, u64 vaddr_lo, 93static bool gm20b_vm_is_pde_in_range(struct vm_gk20a *vm, u64 vaddr_lo,
140 u64 vaddr_hi, u32 pde) 94 u64 vaddr_hi, u32 pde)
141{ 95{
@@ -289,10 +243,6 @@ void gm20b_vm_clear_sparse(struct vm_gk20a *vm, u64 vaddr,
289 vm->mm->pde_stride_shift); 243 vm->mm->pde_stride_shift);
290 244
291 for (pde_i = pde_lo; pde_i <= pde_hi; pde_i++) { 245 for (pde_i = pde_lo; pde_i <= pde_hi; pde_i++) {
292 u32 pte_lo, pte_hi;
293 u32 pte_cur;
294 void *pte_kv_cur;
295
296 struct page_table_gk20a *pte = vm->pdes.ptes[pgsz_idx] + pde_i; 246 struct page_table_gk20a *pte = vm->pdes.ptes[pgsz_idx] + pde_i;
297 pte->ref_cnt--; 247 pte->ref_cnt--;
298 248