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authorTerje Bergstrom <tbergstrom@nvidia.com>2017-03-17 14:09:44 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-03-23 11:44:07 -0400
commit4492c62ffe9398bd4457f6f1c2773e40afe909fb (patch)
tree5d792f81d97844278f4eca665a8b4778fa93dc35 /drivers/gpu/nvgpu/gm20b/mm_gm20b.c
parent33f637585ecd617a9f4423f56e2aa6df0691ac64 (diff)
gpu: nvgpu: Add bus HAL
Add bus HAL and move all bus related hardware sequencing to that file: BAR1 binding, timer access, and interrupt handling. Change-Id: Ibc5f5797dc338de10749b446a7bdbcae600fecb4 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/1323353 Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/mm_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/mm_gm20b.c34
1 files changed, 0 insertions, 34 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
index 18f9eec1..949a5c5d 100644
--- a/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/mm_gm20b.c
@@ -13,17 +13,12 @@
13 * more details. 13 * more details.
14 */ 14 */
15 15
16#include <linux/delay.h>
17
18#include "gk20a/gk20a.h" 16#include "gk20a/gk20a.h"
19 17
20#include "mm_gm20b.h" 18#include "mm_gm20b.h"
21 19
22#include <nvgpu/timers.h>
23
24#include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h> 20#include <nvgpu/hw/gm20b/hw_gmmu_gm20b.h>
25#include <nvgpu/hw/gm20b/hw_ram_gm20b.h> 21#include <nvgpu/hw/gm20b/hw_ram_gm20b.h>
26#include <nvgpu/hw/gm20b/hw_bus_gm20b.h>
27 22
28static void gm20b_mm_set_big_page_size(struct gk20a *g, 23static void gm20b_mm_set_big_page_size(struct gk20a *g,
29 struct mem_desc *mem, int size) 24 struct mem_desc *mem, int size)
@@ -55,34 +50,6 @@ static bool gm20b_mm_support_sparse(struct gk20a *g)
55 return true; 50 return true;
56} 51}
57 52
58static int gm20b_mm_bar1_bind(struct gk20a *g, struct mem_desc *bar1_inst)
59{
60 int retry = 1000;
61 u64 iova = gk20a_mm_inst_block_addr(g, bar1_inst);
62 u32 ptr_v = (u32)(iova >> bar1_instance_block_shift_gk20a());
63
64 gk20a_dbg_info("bar1 inst block ptr: 0x%08x", ptr_v);
65
66 gk20a_writel(g, bus_bar1_block_r(),
67 gk20a_aperture_mask(g, bar1_inst,
68 bus_bar1_block_target_sys_mem_ncoh_f(),
69 bus_bar1_block_target_vid_mem_f()) |
70 bus_bar1_block_mode_virtual_f() |
71 bus_bar1_block_ptr_f(ptr_v));
72 do {
73 u32 val = gk20a_readl(g, bus_bind_status_r());
74 u32 pending = bus_bind_status_bar1_pending_v(val);
75 u32 outstanding = bus_bind_status_bar1_outstanding_v(val);
76 if (!pending && !outstanding)
77 break;
78
79 udelay(5);
80 retry--;
81 } while (retry >= 0 || !tegra_platform_is_silicon());
82
83 return retry ? -EINVAL : 0;
84}
85
86static bool gm20b_mm_is_bar1_supported(struct gk20a *g) 53static bool gm20b_mm_is_bar1_supported(struct gk20a *g)
87{ 54{
88 return true; 55 return true;
@@ -107,7 +74,6 @@ void gm20b_init_mm(struct gpu_ops *gops)
107 gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels; 74 gops->mm.get_mmu_levels = gk20a_mm_get_mmu_levels;
108 gops->mm.init_pdb = gk20a_mm_init_pdb; 75 gops->mm.init_pdb = gk20a_mm_init_pdb;
109 gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw; 76 gops->mm.init_mm_setup_hw = gk20a_init_mm_setup_hw;
110 gops->mm.bar1_bind = gm20b_mm_bar1_bind;
111 gops->mm.is_bar1_supported = gm20b_mm_is_bar1_supported; 77 gops->mm.is_bar1_supported = gm20b_mm_is_bar1_supported;
112 gops->mm.init_inst_block = gk20a_init_inst_block; 78 gops->mm.init_inst_block = gk20a_init_inst_block;
113 gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending; 79 gops->mm.mmu_fault_pending = gk20a_fifo_mmu_fault_pending;