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authorAlex Waterman <alexw@nvidia.com>2016-10-28 20:03:37 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-01-11 15:44:14 -0500
commit7989012df274ba166171ac652cf80fe61993c292 (patch)
tree98bcd78940f6d4c09c28efdef834cfa536a9ce3c /drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
parentb928f10d37bdb57266569073d8b5d553dbf39044 (diff)
gpu: nvgpu: Move gm20b HW headers
Move the gm20b HW headers to a new directory specially for them: include/nvgpu/hw/gm20b And change the code to include like so: #include <nvgpu/hw/gm20b/hw_fb_gm20b.h> This is part of the process to restructure the nvgpu driver. Bug 1799159 Change-Id: I0765e2f6bcd5aa1e803efd250056de3cf9bfa7ed Signed-off-by: Alex Waterman <alexw@nvidia.com> Reviewed-on: http://git-master/r/1244791 GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h497
1 files changed, 0 insertions, 497 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
deleted file mode 100644
index e923e451..00000000
--- a/drivers/gpu/nvgpu/gm20b/hw_trim_gm20b.h
+++ /dev/null
@@ -1,497 +0,0 @@
1/*
2 * Copyright (c) 2014, NVIDIA CORPORATION. All rights reserved.
3 *
4 * This program is free software; you can redistribute it and/or modify it
5 * under the terms and conditions of the GNU General Public License,
6 * version 2, as published by the Free Software Foundation.
7 *
8 * This program is distributed in the hope it will be useful, but WITHOUT
9 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
10 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
11 * more details.
12 *
13 * You should have received a copy of the GNU General Public License
14 * along with this program. If not, see <http://www.gnu.org/licenses/>.
15 */
16/*
17 * Function naming determines intended use:
18 *
19 * <x>_r(void) : Returns the offset for register <x>.
20 *
21 * <x>_o(void) : Returns the offset for element <x>.
22 *
23 * <x>_w(void) : Returns the word offset for word (4 byte) element <x>.
24 *
25 * <x>_<y>_s(void) : Returns size of field <y> of register <x> in bits.
26 *
27 * <x>_<y>_f(u32 v) : Returns a value based on 'v' which has been shifted
28 * and masked to place it at field <y> of register <x>. This value
29 * can be |'d with others to produce a full register value for
30 * register <x>.
31 *
32 * <x>_<y>_m(void) : Returns a mask for field <y> of register <x>. This
33 * value can be ~'d and then &'d to clear the value of field <y> for
34 * register <x>.
35 *
36 * <x>_<y>_<z>_f(void) : Returns the constant value <z> after being shifted
37 * to place it at field <y> of register <x>. This value can be |'d
38 * with others to produce a full register value for <x>.
39 *
40 * <x>_<y>_v(u32 r) : Returns the value of field <y> from a full register
41 * <x> value 'r' after being shifted to place its LSB at bit 0.
42 * This value is suitable for direct comparison with other unshifted
43 * values appropriate for use in field <y> of register <x>.
44 *
45 * <x>_<y>_<z>_v(void) : Returns the constant value for <z> defined for
46 * field <y> of register <x>. This value is suitable for direct
47 * comparison with unshifted values appropriate for use in field <y>
48 * of register <x>.
49 */
50#ifndef _hw_trim_gm20b_h_
51#define _hw_trim_gm20b_h_
52
53static inline u32 trim_sys_gpcpll_cfg_r(void)
54{
55 return 0x00137000;
56}
57static inline u32 trim_sys_gpcpll_cfg_enable_m(void)
58{
59 return 0x1 << 0;
60}
61static inline u32 trim_sys_gpcpll_cfg_enable_v(u32 r)
62{
63 return (r >> 0) & 0x1;
64}
65static inline u32 trim_sys_gpcpll_cfg_enable_no_f(void)
66{
67 return 0x0;
68}
69static inline u32 trim_sys_gpcpll_cfg_enable_yes_f(void)
70{
71 return 0x1;
72}
73static inline u32 trim_sys_gpcpll_cfg_iddq_m(void)
74{
75 return 0x1 << 1;
76}
77static inline u32 trim_sys_gpcpll_cfg_iddq_v(u32 r)
78{
79 return (r >> 1) & 0x1;
80}
81static inline u32 trim_sys_gpcpll_cfg_iddq_power_on_v(void)
82{
83 return 0x00000000;
84}
85static inline u32 trim_sys_gpcpll_cfg_sync_mode_m(void)
86{
87 return 0x1 << 2;
88}
89static inline u32 trim_sys_gpcpll_cfg_sync_mode_v(u32 r)
90{
91 return (r >> 2) & 0x1;
92}
93static inline u32 trim_sys_gpcpll_cfg_sync_mode_enable_f(void)
94{
95 return 0x4;
96}
97static inline u32 trim_sys_gpcpll_cfg_sync_mode_disable_f(void)
98{
99 return 0x0;
100}
101static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_m(void)
102{
103 return 0x1 << 4;
104}
105static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_on_f(void)
106{
107 return 0x0;
108}
109static inline u32 trim_sys_gpcpll_cfg_enb_lckdet_power_off_f(void)
110{
111 return 0x10;
112}
113static inline u32 trim_sys_gpcpll_cfg_pll_lock_v(u32 r)
114{
115 return (r >> 17) & 0x1;
116}
117static inline u32 trim_sys_gpcpll_cfg_pll_lock_true_f(void)
118{
119 return 0x20000;
120}
121static inline u32 trim_sys_gpcpll_coeff_r(void)
122{
123 return 0x00137004;
124}
125static inline u32 trim_sys_gpcpll_coeff_mdiv_f(u32 v)
126{
127 return (v & 0xff) << 0;
128}
129static inline u32 trim_sys_gpcpll_coeff_mdiv_m(void)
130{
131 return 0xff << 0;
132}
133static inline u32 trim_sys_gpcpll_coeff_mdiv_v(u32 r)
134{
135 return (r >> 0) & 0xff;
136}
137static inline u32 trim_sys_gpcpll_coeff_ndiv_f(u32 v)
138{
139 return (v & 0xff) << 8;
140}
141static inline u32 trim_sys_gpcpll_coeff_ndiv_m(void)
142{
143 return 0xff << 8;
144}
145static inline u32 trim_sys_gpcpll_coeff_ndiv_v(u32 r)
146{
147 return (r >> 8) & 0xff;
148}
149static inline u32 trim_sys_gpcpll_coeff_pldiv_f(u32 v)
150{
151 return (v & 0x3f) << 16;
152}
153static inline u32 trim_sys_gpcpll_coeff_pldiv_m(void)
154{
155 return 0x3f << 16;
156}
157static inline u32 trim_sys_gpcpll_coeff_pldiv_v(u32 r)
158{
159 return (r >> 16) & 0x3f;
160}
161static inline u32 trim_sys_sel_vco_r(void)
162{
163 return 0x00137100;
164}
165static inline u32 trim_sys_sel_vco_gpc2clk_out_m(void)
166{
167 return 0x1 << 0;
168}
169static inline u32 trim_sys_sel_vco_gpc2clk_out_init_v(void)
170{
171 return 0x00000000;
172}
173static inline u32 trim_sys_sel_vco_gpc2clk_out_init_f(void)
174{
175 return 0x0;
176}
177static inline u32 trim_sys_sel_vco_gpc2clk_out_bypass_f(void)
178{
179 return 0x0;
180}
181static inline u32 trim_sys_sel_vco_gpc2clk_out_vco_f(void)
182{
183 return 0x1;
184}
185static inline u32 trim_sys_gpc2clk_out_r(void)
186{
187 return 0x00137250;
188}
189static inline u32 trim_sys_gpc2clk_out_bypdiv_s(void)
190{
191 return 6;
192}
193static inline u32 trim_sys_gpc2clk_out_bypdiv_f(u32 v)
194{
195 return (v & 0x3f) << 0;
196}
197static inline u32 trim_sys_gpc2clk_out_bypdiv_m(void)
198{
199 return 0x3f << 0;
200}
201static inline u32 trim_sys_gpc2clk_out_bypdiv_v(u32 r)
202{
203 return (r >> 0) & 0x3f;
204}
205static inline u32 trim_sys_gpc2clk_out_bypdiv_by31_f(void)
206{
207 return 0x3c;
208}
209static inline u32 trim_sys_gpc2clk_out_vcodiv_s(void)
210{
211 return 6;
212}
213static inline u32 trim_sys_gpc2clk_out_vcodiv_f(u32 v)
214{
215 return (v & 0x3f) << 8;
216}
217static inline u32 trim_sys_gpc2clk_out_vcodiv_m(void)
218{
219 return 0x3f << 8;
220}
221static inline u32 trim_sys_gpc2clk_out_vcodiv_v(u32 r)
222{
223 return (r >> 8) & 0x3f;
224}
225static inline u32 trim_sys_gpc2clk_out_vcodiv_by1_f(void)
226{
227 return 0x0;
228}
229static inline u32 trim_sys_gpc2clk_out_sdiv14_m(void)
230{
231 return 0x1 << 31;
232}
233static inline u32 trim_sys_gpc2clk_out_sdiv14_indiv4_mode_f(void)
234{
235 return 0x80000000;
236}
237static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_r(u32 i)
238{
239 return 0x00134124 + i*512;
240}
241static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_noofipclks_f(u32 v)
242{
243 return (v & 0x3fff) << 0;
244}
245static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_write_en_asserted_f(void)
246{
247 return 0x10000;
248}
249static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_enable_asserted_f(void)
250{
251 return 0x100000;
252}
253static inline u32 trim_gpc_clk_cntr_ncgpcclk_cfg_reset_asserted_f(void)
254{
255 return 0x1000000;
256}
257static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_r(u32 i)
258{
259 return 0x00134128 + i*512;
260}
261static inline u32 trim_gpc_clk_cntr_ncgpcclk_cnt_value_v(u32 r)
262{
263 return (r >> 0) & 0xfffff;
264}
265static inline u32 trim_sys_gpcpll_cfg2_r(void)
266{
267 return 0x0013700c;
268}
269static inline u32 trim_sys_gpcpll_cfg2_sdm_din_f(u32 v)
270{
271 return (v & 0xff) << 0;
272}
273static inline u32 trim_sys_gpcpll_cfg2_sdm_din_m(void)
274{
275 return 0xff << 0;
276}
277static inline u32 trim_sys_gpcpll_cfg2_sdm_din_v(u32 r)
278{
279 return (r >> 0) & 0xff;
280}
281static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_f(u32 v)
282{
283 return (v & 0xff) << 8;
284}
285static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_m(void)
286{
287 return 0xff << 8;
288}
289static inline u32 trim_sys_gpcpll_cfg2_sdm_din_new_v(u32 r)
290{
291 return (r >> 8) & 0xff;
292}
293static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_f(u32 v)
294{
295 return (v & 0xff) << 24;
296}
297static inline u32 trim_sys_gpcpll_cfg2_pll_stepa_m(void)
298{
299 return 0xff << 24;
300}
301static inline u32 trim_sys_gpcpll_cfg3_r(void)
302{
303 return 0x00137018;
304}
305static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_f(u32 v)
306{
307 return (v & 0x1ff) << 0;
308}
309static inline u32 trim_sys_gpcpll_cfg3_vco_ctrl_m(void)
310{
311 return 0x1ff << 0;
312}
313static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_f(u32 v)
314{
315 return (v & 0xff) << 16;
316}
317static inline u32 trim_sys_gpcpll_cfg3_pll_stepb_m(void)
318{
319 return 0xff << 16;
320}
321static inline u32 trim_sys_gpcpll_cfg3_dfs_testout_v(u32 r)
322{
323 return (r >> 24) & 0x7f;
324}
325static inline u32 trim_sys_gpcpll_dvfs0_r(void)
326{
327 return 0x00137010;
328}
329static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_f(u32 v)
330{
331 return (v & 0x7f) << 0;
332}
333static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_m(void)
334{
335 return 0x7f << 0;
336}
337static inline u32 trim_sys_gpcpll_dvfs0_dfs_coeff_v(u32 r)
338{
339 return (r >> 0) & 0x7f;
340}
341static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_f(u32 v)
342{
343 return (v & 0x7f) << 8;
344}
345static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_m(void)
346{
347 return 0x7f << 8;
348}
349static inline u32 trim_sys_gpcpll_dvfs0_dfs_det_max_v(u32 r)
350{
351 return (r >> 8) & 0x7f;
352}
353static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_f(u32 v)
354{
355 return (v & 0x3f) << 16;
356}
357static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_m(void)
358{
359 return 0x3f << 16;
360}
361static inline u32 trim_sys_gpcpll_dvfs0_dfs_dc_offset_v(u32 r)
362{
363 return (r >> 16) & 0x3f;
364}
365static inline u32 trim_sys_gpcpll_dvfs0_mode_m(void)
366{
367 return 0x1 << 28;
368}
369static inline u32 trim_sys_gpcpll_dvfs0_mode_dvfspll_f(void)
370{
371 return 0x0;
372}
373static inline u32 trim_sys_gpcpll_dvfs1_r(void)
374{
375 return 0x00137014;
376}
377static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_f(u32 v)
378{
379 return (v & 0x7f) << 0;
380}
381static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_m(void)
382{
383 return 0x7f << 0;
384}
385static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_det_v(u32 r)
386{
387 return (r >> 0) & 0x7f;
388}
389static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_strb_m(void)
390{
391 return 0x1 << 7;
392}
393static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_f(u32 v)
394{
395 return (v & 0x7f) << 8;
396}
397static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_m(void)
398{
399 return 0x7f << 8;
400}
401static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_cal_v(u32 r)
402{
403 return (r >> 8) & 0x7f;
404}
405static inline u32 trim_sys_gpcpll_dvfs1_dfs_ext_sel_m(void)
406{
407 return 0x1 << 15;
408}
409static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_f(u32 v)
410{
411 return (v & 0xfff) << 16;
412}
413static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_m(void)
414{
415 return 0xfff << 16;
416}
417static inline u32 trim_sys_gpcpll_dvfs1_dfs_ctrl_v(u32 r)
418{
419 return (r >> 16) & 0xfff;
420}
421static inline u32 trim_sys_gpcpll_dvfs1_en_sdm_m(void)
422{
423 return 0x1 << 28;
424}
425static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_m(void)
426{
427 return 0x1 << 29;
428}
429static inline u32 trim_sys_gpcpll_dvfs1_en_dfs_cal_m(void)
430{
431 return 0x1 << 30;
432}
433static inline u32 trim_sys_gpcpll_dvfs1_dfs_cal_done_v(u32 r)
434{
435 return (r >> 31) & 0x1;
436}
437static inline u32 trim_sys_gpcpll_dvfs2_r(void)
438{
439 return 0x00137020;
440}
441static inline u32 trim_sys_gpcpll_ndiv_slowdown_r(void)
442{
443 return 0x0013701c;
444}
445static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_m(void)
446{
447 return 0x1 << 22;
448}
449static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_yes_f(void)
450{
451 return 0x400000;
452}
453static inline u32 trim_sys_gpcpll_ndiv_slowdown_slowdown_using_pll_no_f(void)
454{
455 return 0x0;
456}
457static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_m(void)
458{
459 return 0x1 << 31;
460}
461static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_yes_f(void)
462{
463 return 0x80000000;
464}
465static inline u32 trim_sys_gpcpll_ndiv_slowdown_en_dynramp_no_f(void)
466{
467 return 0x0;
468}
469static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_r(void)
470{
471 return 0x001328a0;
472}
473static inline u32 trim_gpc_bcast_gpcpll_ndiv_slowdown_debug_pll_dynramp_done_synced_v(u32 r)
474{
475 return (r >> 24) & 0x1;
476}
477static inline u32 trim_gpc_bcast_gpcpll_dvfs2_r(void)
478{
479 return 0x00132820;
480}
481static inline u32 trim_sys_bypassctrl_r(void)
482{
483 return 0x00137340;
484}
485static inline u32 trim_sys_bypassctrl_gpcpll_m(void)
486{
487 return 0x1 << 0;
488}
489static inline u32 trim_sys_bypassctrl_gpcpll_bypassclk_f(void)
490{
491 return 0x1;
492}
493static inline u32 trim_sys_bypassctrl_gpcpll_vco_f(void)
494{
495 return 0x0;
496}
497#endif
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