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authorTerje Bergstrom <tbergstrom@nvidia.com>2014-10-27 03:16:51 -0400
committerDan Willemsen <dwillemsen@nvidia.com>2015-03-18 15:11:52 -0400
commit4739499f07b29282ee1031d08adaa76c238da2a6 (patch)
tree10caa152eea6250e46cad6172553069b4bb3dcb9 /drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h
parentb5bb4f53dbdde8473e1160d4522c5d9da55f115f (diff)
gpu: nvgpu: Sync gk20a and gm20b headers
Synchronize gk20a and gm20b headers. All registers which were added to gk20a are now added to gm20b, and some registers that are unused are removed. Bug 1567274 Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680 Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-on: http://git-master/r/590313 GVS: Gerrit_Virtual_Submit
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h56
1 files changed, 0 insertions, 56 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h
index 09bd5830..d928d70e 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_therm_gm20b.h
@@ -66,66 +66,10 @@ static inline u32 therm_evt_ext_therm_2_r(void)
66{ 66{
67 return 0x00020708; 67 return 0x00020708;
68} 68}
69static inline u32 therm_evt_ba_w0_t1h_r(void)
70{
71 return 0x00020750;
72}
73static inline u32 therm_weight_1_r(void) 69static inline u32 therm_weight_1_r(void)
74{ 70{
75 return 0x00020024; 71 return 0x00020024;
76} 72}
77static inline u32 therm_peakpower_config1_r(u32 i)
78{
79 return 0x00020154 + i*4;
80}
81static inline u32 therm_peakpower_config1_window_period_2m_v(void)
82{
83 return 0x0000000f;
84}
85static inline u32 therm_peakpower_config1_window_period_2m_f(void)
86{
87 return 0xf;
88}
89static inline u32 therm_peakpower_config1_window_en_enabled_f(void)
90{
91 return 0x80000000;
92}
93static inline u32 therm_peakpower_config8_r(u32 i)
94{
95 return 0x000202e8 + i*4;
96}
97static inline u32 therm_peakpower_config8_ba_sum_shift_s(void)
98{
99 return 5;
100}
101static inline u32 therm_peakpower_config8_ba_sum_shift_f(u32 v)
102{
103 return (v & 0x1f) << 8;
104}
105static inline u32 therm_peakpower_config8_ba_sum_shift_m(void)
106{
107 return 0x1f << 8;
108}
109static inline u32 therm_peakpower_config8_ba_sum_shift_v(u32 r)
110{
111 return (r >> 8) & 0x1f;
112}
113static inline u32 therm_peakpower_config2_r(u32 i)
114{
115 return 0x00020170 + i*4;
116}
117static inline u32 therm_peakpower_config4_r(u32 i)
118{
119 return 0x000201c0 + i*4;
120}
121static inline u32 therm_peakpower_config6_r(u32 i)
122{
123 return 0x00020270 + i*4;
124}
125static inline u32 therm_peakpower_config9_r(u32 i)
126{
127 return 0x000202f4 + i*4;
128}
129static inline u32 therm_config1_r(void) 73static inline u32 therm_config1_r(void)
130{ 74{
131 return 0x00020050; 75 return 0x00020050;