gpu: nvgpu: Sync gk20a and gm20b headers

Synchronize gk20a and gm20b headers. All registers which were added
to gk20a are now added to gm20b, and some registers that are unused
are removed.

Bug 1567274

Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590313
GVS: Gerrit_Virtual_Submit

1 files changed, 41 insertions, 1 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h
index 2e1df1d4..a05f1c2b 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_ram_gm20b.h
@@ -338,7 +338,7 @@ static inline u32 ram_fc_chid_id_w(void)
 {
         return 0;
 }
-static inline u32 ram_fc_pb_timeslice_w(void)
+static inline u32 ram_fc_runlist_timeslice_w(void)
 {
         return 62;
 }
@@ -402,4 +402,44 @@ static inline u32 ram_rl_entry_size_v(void)
 {
         return 0x00000008;
 }
+static inline u32 ram_rl_entry_chid_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_id_f(u32 v)
+{
+        return (v & 0xfff) << 0;
+}
+static inline u32 ram_rl_entry_type_f(u32 v)
+{
+        return (v & 0x1) << 13;
+}
+static inline u32 ram_rl_entry_type_chid_f(void)
+{
+        return 0x0;
+}
+static inline u32 ram_rl_entry_type_tsg_f(void)
+{
+        return 0x2000;
+}
+static inline u32 ram_rl_entry_timeslice_scale_f(u32 v)
+{
+        return (v & 0xf) << 14;
+}
+static inline u32 ram_rl_entry_timeslice_scale_3_f(void)
+{
+        return 0xc000;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_f(u32 v)
+{
+        return (v & 0xff) << 18;
+}
+static inline u32 ram_rl_entry_timeslice_timeout_128_f(void)
+{
+        return 0x2000000;
+}
+static inline u32 ram_rl_entry_tsg_length_f(u32 v)
+{
+        return (v & 0x3f) << 26;
+}
 #endif