gpu: nvgpu: Sync gk20a and gm20b headers

Synchronize gk20a and gm20b headers. All registers which were added
to gk20a are now added to gm20b, and some registers that are unused
are removed.

Bug 1567274

Change-Id: Ia3b7958c148e495cbff420ee56bb448db0f58680
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
Reviewed-on: http://git-master/r/590313
GVS: Gerrit_Virtual_Submit

1 files changed, 54 insertions, 10 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h
index 1b741677..96e21899 100644
--- a/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/hw_mc_gm20b.h
@@ -50,31 +50,47 @@
 #ifndef _hw_mc_gm20b_h_
 #define _hw_mc_gm20b_h_
 
-static inline u32 mc_intr_0_r(void)
+static inline u32 mc_boot_0_r(void)
 {
-        return 0x00000100;
+        return 0x00000000;
 }
-static inline u32 mc_intr_0_pfifo_pending_f(void)
+static inline u32 mc_boot_0_architecture_v(u32 r)
 {
-        return 0x100;
+        return (r >> 24) & 0x1f;
 }
-static inline u32 mc_intr_0_pgraph_pending_f(void)
+static inline u32 mc_boot_0_implementation_v(u32 r)
 {
-        return 0x1000;
+        return (r >> 20) & 0xf;
+}
+static inline u32 mc_boot_0_major_revision_v(u32 r)
+{
+        return (r >> 4) & 0xf;
+}
+static inline u32 mc_boot_0_minor_revision_v(u32 r)
+{
+        return (r >> 0) & 0xf;
 }
-static inline u32 mc_intr_0_pmu_pending_f(void)
+static inline u32 mc_intr_r(u32 i)
+{
+        return 0x00000100 + i*4;
+}
+static inline u32 mc_intr_pfifo_pending_f(void)
+{
+        return 0x100;
+}
+static inline u32 mc_intr_pmu_pending_f(void)
 {
         return 0x1000000;
 }
-static inline u32 mc_intr_0_ltc_pending_f(void)
+static inline u32 mc_intr_ltc_pending_f(void)
 {
         return 0x2000000;
 }
-static inline u32 mc_intr_0_priv_ring_pending_f(void)
+static inline u32 mc_intr_priv_ring_pending_f(void)
 {
         return 0x40000000;
 }
-static inline u32 mc_intr_0_pbus_pending_f(void)
+static inline u32 mc_intr_pbus_pending_f(void)
 {
         return 0x10000000;
 }
@@ -98,6 +114,30 @@ static inline u32 mc_intr_en_0_inta_hardware_f(void)
 {
         return 0x1;
 }
+static inline u32 mc_intr_mask_1_r(void)
+{
+        return 0x00000644;
+}
+static inline u32 mc_intr_mask_1_pmu_s(void)
+{
+        return 1;
+}
+static inline u32 mc_intr_mask_1_pmu_f(u32 v)
+{
+        return (v & 0x1) << 24;
+}
+static inline u32 mc_intr_mask_1_pmu_m(void)
+{
+        return 0x1 << 24;
+}
+static inline u32 mc_intr_mask_1_pmu_v(u32 r)
+{
+        return (r >> 24) & 0x1;
+}
+static inline u32 mc_intr_mask_1_pmu_enabled_f(void)
+{
+        return 0x1000000;
+}
 static inline u32 mc_intr_en_1_r(void)
 {
         return 0x00000144;
@@ -106,6 +146,10 @@ static inline u32 mc_intr_en_1_inta_disabled_f(void)
 {
         return 0x0;
 }
+static inline u32 mc_intr_en_1_inta_hardware_f(void)
+{
+        return 0x1;
+}
 static inline u32 mc_enable_r(void)
 {
         return 0x00000200;