diff options
author | sujeet baranwal <sbaranwal@nvidia.com> | 2015-03-02 18:36:22 -0500 |
---|---|---|
committer | Dan Willemsen <dwillemsen@nvidia.com> | 2015-04-04 21:58:04 -0400 |
commit | 895675e1d5790e2361b22edb50d702f7dd9a8edd (patch) | |
tree | dbe3586cec5351fd2c2eb13d91c258e663d73b08 /drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |
parent | cf0085ec231246748b34081d2786c29cedcbd706 (diff) |
gpu: nvgpu: Removal of regops from CUDA driver
The current CUDA drivers have been using the regops to
directly accessing the GPU registers from user space through
the dbg node. This is a security hole and needs to be avoided.
The patch alternatively implements the similar functionality
in the kernel and provide an ioctl for it.
Bug 200083334
Change-Id: Ic5ff5a215cbabe7a46837bc4e15efcceb0df0367
Signed-off-by: sujeet baranwal <sbaranwal@nvidia.com>
Reviewed-on: http://git-master/r/711758
Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com>
Tested-by: Terje Bergstrom <tbergstrom@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | 68 |
1 files changed, 68 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h index 868b8fe7..11605deb 100644 --- a/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/hw_gr_gm20b.h | |||
@@ -330,6 +330,30 @@ static inline u32 gr_activity_4_r(void) | |||
330 | { | 330 | { |
331 | return 0x00400390; | 331 | return 0x00400390; |
332 | } | 332 | } |
333 | static inline u32 gr_pri_gpc0_gcc_dbg_r(void) | ||
334 | { | ||
335 | return 0x00501000; | ||
336 | } | ||
337 | static inline u32 gr_pri_gpcs_gcc_dbg_r(void) | ||
338 | { | ||
339 | return 0x00419000; | ||
340 | } | ||
341 | static inline u32 gr_pri_gpcs_gcc_dbg_invalidate_m(void) | ||
342 | { | ||
343 | return 0x1 << 1; | ||
344 | } | ||
345 | static inline u32 gr_pri_gpc0_tpc0_sm_cache_control_r(void) | ||
346 | { | ||
347 | return 0x005046a4; | ||
348 | } | ||
349 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_r(void) | ||
350 | { | ||
351 | return 0x00419ea4; | ||
352 | } | ||
353 | static inline u32 gr_pri_gpcs_tpcs_sm_cache_control_invalidate_cache_m(void) | ||
354 | { | ||
355 | return 0x1 << 0; | ||
356 | } | ||
333 | static inline u32 gr_pri_sked_activity_r(void) | 357 | static inline u32 gr_pri_sked_activity_r(void) |
334 | { | 358 | { |
335 | return 0x00407054; | 359 | return 0x00407054; |
@@ -2998,6 +3022,10 @@ static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_enabled_f(void) | |||
2998 | { | 3022 | { |
2999 | return 0x2; | 3023 | return 0x2; |
3000 | } | 3024 | } |
3025 | static inline u32 gr_gpc0_tpc0_tpccs_tpc_exception_en_sm_v(u32 r) | ||
3026 | { | ||
3027 | return (r >> 1) & 0x1; | ||
3028 | } | ||
3001 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) | 3029 | static inline u32 gr_gpcs_gpccs_gpc_exception_en_r(void) |
3002 | { | 3030 | { |
3003 | return 0x0041ac94; | 3031 | return 0x0041ac94; |
@@ -3054,10 +3082,50 @@ static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_run_trigger_task_f(void) | |||
3054 | { | 3082 | { |
3055 | return 0x40000000; | 3083 | return 0x40000000; |
3056 | } | 3084 | } |
3085 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_v(u32 r) | ||
3086 | { | ||
3087 | return (r >> 1) & 0x1; | ||
3088 | } | ||
3089 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_warp_disable_f(void) | ||
3090 | { | ||
3091 | return 0x0; | ||
3092 | } | ||
3093 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_v(u32 r) | ||
3094 | { | ||
3095 | return (r >> 2) & 0x1; | ||
3096 | } | ||
3097 | static inline u32 gr_gpc0_tpc0_sm_dbgr_control0_stop_on_any_sm_disable_f(void) | ||
3098 | { | ||
3099 | return 0x0; | ||
3100 | } | ||
3101 | static inline u32 gr_gpc0_tpc0_sm_warp_valid_mask_r(void) | ||
3102 | { | ||
3103 | return 0x00504614; | ||
3104 | } | ||
3105 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_pause_mask_r(void) | ||
3106 | { | ||
3107 | return 0x00504624; | ||
3108 | } | ||
3109 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_r(void) | ||
3110 | { | ||
3111 | return 0x00504634; | ||
3112 | } | ||
3113 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_warp_disable_v(void) | ||
3114 | { | ||
3115 | return 0x00000000; | ||
3116 | } | ||
3117 | static inline u32 gr_gpc0_tpc0_sm_dbgr_bpt_trap_mask_stop_on_any_sm_disable_v(void) | ||
3118 | { | ||
3119 | return 0x00000000; | ||
3120 | } | ||
3057 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) | 3121 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_r(void) |
3058 | { | 3122 | { |
3059 | return 0x0050460c; | 3123 | return 0x0050460c; |
3060 | } | 3124 | } |
3125 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_sm_in_trap_mode_v(u32 r) | ||
3126 | { | ||
3127 | return (r >> 0) & 0x1; | ||
3128 | } | ||
3061 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) | 3129 | static inline u32 gr_gpc0_tpc0_sm_dbgr_status0_locked_down_v(u32 r) |
3062 | { | 3130 | { |
3063 | return (r >> 4) & 0x1; | 3131 | return (r >> 4) & 0x1; |