gpu: nvgpu: CONFIG_TEGRA_ACR is supported by default

TEGRA_ACR config is supposed to be enabled maxwell
onwards. Since gk20a support is no longer supported,
delete code that is not under TEGRA_ACR config

Change-Id: Id52485680bca1ceaadcb94f9603c0898c2002e02
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595437
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 0 insertions, 16 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 227b6b6c..bb18d2d7 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -634,7 +634,6 @@ int gm20b_init_hal(struct gk20a *g)
         __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false);
         __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false);
 
-#ifdef CONFIG_TEGRA_ACR
         if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
                 __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
         } else {
@@ -646,21 +645,6 @@ int gm20b_init_hal(struct gk20a *g)
                         __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
                 }
         }
-#else
-        if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) {
-                gk20a_dbg_info("running ASIM with PRIV security disabled");
-                __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-        } else {
-                val = gk20a_readl(g, fuse_opt_priv_sec_en_r());
-                if (!val) {
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false);
-                } else {
-                        gk20a_dbg_info("priv security is not supported but enabled");
-                        __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true);
-                        return -EPERM;
-                }
-        }
-#endif
 
         /* priv security dependent ops */
         if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) {