diff options
author | Sunny He <suhe@nvidia.com> | 2017-07-24 15:18:38 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-26 05:45:14 -0400 |
commit | d59271c7b79080388371877fc2d10574ca42206a (patch) | |
tree | 921f6d1ddce07235d7fbd1f27e6510b8cfe56ae7 /drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |
parent | de3ad1a94974b08268a485136f04b8e436ef2579 (diff) |
gpu: nvgpu: Remove privsecurity flag from gpu_ops
Replace privsecurity boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_PRIVSECURITY
Jira NVGPU-74
Change-Id: I4b258f5ffbe30a6344ffba0ece51c6f5d47ebec1
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1525713
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hal_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 16 |
1 files changed, 8 insertions, 8 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 01e277ce..228e1a97 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -356,38 +356,38 @@ int gm20b_init_hal(struct gk20a *g) | |||
356 | 356 | ||
357 | #ifdef CONFIG_TEGRA_ACR | 357 | #ifdef CONFIG_TEGRA_ACR |
358 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 358 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
359 | gops->privsecurity = 1; | 359 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
360 | } else { | 360 | } else { |
361 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 361 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
362 | if (!val) { | 362 | if (!val) { |
363 | gk20a_dbg_info("priv security is disabled in HW"); | 363 | gk20a_dbg_info("priv security is disabled in HW"); |
364 | gops->privsecurity = 0; | 364 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
365 | } else { | 365 | } else { |
366 | gops->privsecurity = 1; | 366 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
367 | } | 367 | } |
368 | } | 368 | } |
369 | #else | 369 | #else |
370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 370 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { |
371 | gk20a_dbg_info("running ASIM with PRIV security disabled"); | 371 | gk20a_dbg_info("running ASIM with PRIV security disabled"); |
372 | gops->privsecurity = 0; | 372 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
373 | } else { | 373 | } else { |
374 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | 374 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); |
375 | if (!val) { | 375 | if (!val) { |
376 | gops->privsecurity = 0; | 376 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); |
377 | } else { | 377 | } else { |
378 | gk20a_dbg_info("priv security is not supported but enabled"); | 378 | gk20a_dbg_info("priv security is not supported but enabled"); |
379 | gops->privsecurity = 1; | 379 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); |
380 | return -EPERM; | 380 | return -EPERM; |
381 | } | 381 | } |
382 | } | 382 | } |
383 | #endif | 383 | #endif |
384 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 384 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
385 | gm20b_init_gr(gops); | 385 | gm20b_init_gr(g); |
386 | gm20b_init_fb(gops); | 386 | gm20b_init_fb(gops); |
387 | gm20b_init_ce2(gops); | 387 | gm20b_init_ce2(gops); |
388 | gm20b_init_gr_ctx(gops); | 388 | gm20b_init_gr_ctx(gops); |
389 | gm20b_init_mm(gops); | 389 | gm20b_init_mm(gops); |
390 | gm20b_init_pmu_ops(gops); | 390 | gm20b_init_pmu_ops(g); |
391 | gm20b_init_clk_ops(gops); | 391 | gm20b_init_clk_ops(gops); |
392 | gm20b_init_regops(gops); | 392 | gm20b_init_regops(gops); |
393 | gm20b_init_therm_ops(gops); | 393 | gm20b_init_therm_ops(gops); |