diff options
author | Seema Khowala <seemaj@nvidia.com> | 2017-11-09 17:13:25 -0500 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-11-22 03:59:28 -0500 |
commit | 8fe633449f92d35b60a60de647a4e8fc1b5c8936 (patch) | |
tree | f29ee0ed1c9eba66b99033a17d3b2854662b0a15 /drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |
parent | f34a4d0b125ebf45373e40478925b3eb75b7898a (diff) |
gpu: nvgpu: Add check_priv_security fuse ops
-New fuse ops is added to set NVGPU_SEC_PRIVSECURITY
and NVGPU_SEC_SECUREGPCCS bits in g->enabled_flags
during hal initialization
-For igpu non simulation platforms, fuses are read
to decide if gpu should be allowed to boot or not.
--Do not boot gpu if priv_sec_en is set but wpr_enabled
is not set to 1 or vpr_auto_fetch_disable is not set to 0
--With priv_sec_en set, all falcons have to boot
in LS mode and this needs wpr_enabled set to 1
AND vpr_auto_fetch_disable set to 0. In this case
gmmu tries to pull wpr and vpr settings from tegra mc
Bug 2018223
Change-Id: Iceaa1b0b3214e9a3d6cef5d77a82e034302f748b
Signed-off-by: Seema Khowala <seemaj@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1595454
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hal_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 22 |
1 files changed, 9 insertions, 13 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index bb18d2d7..779dde3d 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -54,6 +54,7 @@ | |||
54 | #include "bus_gm20b.h" | 54 | #include "bus_gm20b.h" |
55 | #include "hal_gm20b.h" | 55 | #include "hal_gm20b.h" |
56 | #include "acr_gm20b.h" | 56 | #include "acr_gm20b.h" |
57 | #include "fuse_gm20b.h" | ||
57 | 58 | ||
58 | #include <nvgpu/debug.h> | 59 | #include <nvgpu/debug.h> |
59 | #include <nvgpu/bug.h> | 60 | #include <nvgpu/bug.h> |
@@ -582,6 +583,9 @@ static const struct gpu_ops gm20b_ops = { | |||
582 | .priv_ring = { | 583 | .priv_ring = { |
583 | .isr = gk20a_priv_ring_isr, | 584 | .isr = gk20a_priv_ring_isr, |
584 | }, | 585 | }, |
586 | .fuse = { | ||
587 | .check_priv_security = gm20b_fuse_check_priv_security, | ||
588 | }, | ||
585 | .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, | 589 | .chip_init_gpu_characteristics = gk20a_init_gpu_characteristics, |
586 | .get_litter_value = gm20b_get_litter_value, | 590 | .get_litter_value = gm20b_get_litter_value, |
587 | }; | 591 | }; |
@@ -589,7 +593,6 @@ static const struct gpu_ops gm20b_ops = { | |||
589 | int gm20b_init_hal(struct gk20a *g) | 593 | int gm20b_init_hal(struct gk20a *g) |
590 | { | 594 | { |
591 | struct gpu_ops *gops = &g->ops; | 595 | struct gpu_ops *gops = &g->ops; |
592 | u32 val; | ||
593 | 596 | ||
594 | gops->ltc = gm20b_ops.ltc; | 597 | gops->ltc = gm20b_ops.ltc; |
595 | gops->ce2 = gm20b_ops.ce2; | 598 | gops->ce2 = gm20b_ops.ce2; |
@@ -625,26 +628,19 @@ int gm20b_init_hal(struct gk20a *g) | |||
625 | 628 | ||
626 | gops->priv_ring = gm20b_ops.priv_ring; | 629 | gops->priv_ring = gm20b_ops.priv_ring; |
627 | 630 | ||
631 | gops->fuse = gm20b_ops.fuse; | ||
632 | |||
628 | /* Lone functions */ | 633 | /* Lone functions */ |
629 | gops->chip_init_gpu_characteristics = | 634 | gops->chip_init_gpu_characteristics = |
630 | gm20b_ops.chip_init_gpu_characteristics; | 635 | gm20b_ops.chip_init_gpu_characteristics; |
631 | gops->get_litter_value = gm20b_ops.get_litter_value; | 636 | gops->get_litter_value = gm20b_ops.get_litter_value; |
632 | 637 | ||
633 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); | 638 | __nvgpu_set_enabled(g, NVGPU_GR_USE_DMA_FOR_FW_BOOTSTRAP, true); |
634 | __nvgpu_set_enabled(g, NVGPU_SEC_SECUREGPCCS, false); | ||
635 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); | 639 | __nvgpu_set_enabled(g, NVGPU_PMU_PSTATE, false); |
636 | 640 | ||
637 | if (nvgpu_is_enabled(g, NVGPU_IS_FMODEL)) { | 641 | /* Read fuses to check if gpu needs to boot in secure/non-secure mode */ |
638 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | 642 | if (gops->fuse.check_priv_security(g)) |
639 | } else { | 643 | return -EINVAL; /* Do not boot gpu */ |
640 | val = gk20a_readl(g, fuse_opt_priv_sec_en_r()); | ||
641 | if (!val) { | ||
642 | gk20a_dbg_info("priv security is disabled in HW"); | ||
643 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, false); | ||
644 | } else { | ||
645 | __nvgpu_set_enabled(g, NVGPU_SEC_PRIVSECURITY, true); | ||
646 | } | ||
647 | } | ||
648 | 644 | ||
649 | /* priv security dependent ops */ | 645 | /* priv security dependent ops */ |
650 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { | 646 | if (nvgpu_is_enabled(g, NVGPU_SEC_PRIVSECURITY)) { |