diff options
author | Sunny He <suhe@nvidia.com> | 2017-06-30 18:53:08 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-24 02:35:06 -0400 |
commit | 66ec347db401affd8bcd425dc123e7162b9ae3bb (patch) | |
tree | cbeb24e465208c6ab3b9527a86ba35003837f176 /drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |
parent | 2b582c5141752ff272c5d059b56433155bc3985a (diff) |
gpu: nvgpu: Reorg fifo HAL initialization
Reorganize HAL initialization to remove inheritance and construct
the gpu_ops struct at compile time. This patch only covers the fifo
sub-module of the gpu_ops struct.
Perform HAL function assignments in hal_gxxxx.c through the
population of a chip-specific copy of gpu_ops.
Jira NVGPU-74
Change-Id: I43d94067a1d7eafba4cdb28311e0ce25812013a7
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1522553
Reviewed-by: Automatic_Commit_Validation_User
GVS: Gerrit_Virtual_Submit
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hal_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/hal_gm20b.c | 66 |
1 files changed, 64 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c index 87acb25c..bdee1149 100644 --- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c | |||
@@ -15,6 +15,7 @@ | |||
15 | 15 | ||
16 | #include "gk20a/gk20a.h" | 16 | #include "gk20a/gk20a.h" |
17 | #include "gk20a/dbg_gpu_gk20a.h" | 17 | #include "gk20a/dbg_gpu_gk20a.h" |
18 | #include "gk20a/fifo_gk20a.h" | ||
18 | #include "gk20a/css_gr_gk20a.h" | 19 | #include "gk20a/css_gr_gk20a.h" |
19 | #include "gk20a/mc_gk20a.h" | 20 | #include "gk20a/mc_gk20a.h" |
20 | #include "gk20a/bus_gk20a.h" | 21 | #include "gk20a/bus_gk20a.h" |
@@ -46,6 +47,9 @@ | |||
46 | 47 | ||
47 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> | 48 | #include <nvgpu/hw/gm20b/hw_proj_gm20b.h> |
48 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> | 49 | #include <nvgpu/hw/gm20b/hw_fuse_gm20b.h> |
50 | #include <nvgpu/hw/gm20b/hw_fifo_gm20b.h> | ||
51 | #include <nvgpu/hw/gm20b/hw_ram_gm20b.h> | ||
52 | #include <nvgpu/hw/gm20b/hw_top_gm20b.h> | ||
49 | 53 | ||
50 | #define PRIV_SECURITY_DISABLE 0x01 | 54 | #define PRIV_SECURITY_DISABLE 0x01 |
51 | 55 | ||
@@ -202,6 +206,64 @@ static const struct gpu_ops gm20b_ops = { | |||
202 | .pg_gr_load_gating_prod = | 206 | .pg_gr_load_gating_prod = |
203 | gr_gm20b_pg_gr_load_gating_prod, | 207 | gr_gm20b_pg_gr_load_gating_prod, |
204 | }, | 208 | }, |
209 | .fifo = { | ||
210 | .init_fifo_setup_hw = gk20a_init_fifo_setup_hw, | ||
211 | .bind_channel = channel_gm20b_bind, | ||
212 | .unbind_channel = gk20a_fifo_channel_unbind, | ||
213 | .disable_channel = gk20a_fifo_disable_channel, | ||
214 | .enable_channel = gk20a_fifo_enable_channel, | ||
215 | .alloc_inst = gk20a_fifo_alloc_inst, | ||
216 | .free_inst = gk20a_fifo_free_inst, | ||
217 | .setup_ramfc = gk20a_fifo_setup_ramfc, | ||
218 | .channel_set_priority = gk20a_fifo_set_priority, | ||
219 | .channel_set_timeslice = gk20a_fifo_set_timeslice, | ||
220 | .default_timeslice_us = gk20a_fifo_default_timeslice_us, | ||
221 | .setup_userd = gk20a_fifo_setup_userd, | ||
222 | .userd_gp_get = gk20a_fifo_userd_gp_get, | ||
223 | .userd_gp_put = gk20a_fifo_userd_gp_put, | ||
224 | .userd_pb_get = gk20a_fifo_userd_pb_get, | ||
225 | .pbdma_acquire_val = gk20a_fifo_pbdma_acquire_val, | ||
226 | .preempt_channel = gk20a_fifo_preempt_channel, | ||
227 | .preempt_tsg = gk20a_fifo_preempt_tsg, | ||
228 | .update_runlist = gk20a_fifo_update_runlist, | ||
229 | .trigger_mmu_fault = gm20b_fifo_trigger_mmu_fault, | ||
230 | .get_mmu_fault_info = gk20a_fifo_get_mmu_fault_info, | ||
231 | .wait_engine_idle = gk20a_fifo_wait_engine_idle, | ||
232 | .get_num_fifos = gm20b_fifo_get_num_fifos, | ||
233 | .get_pbdma_signature = gk20a_fifo_get_pbdma_signature, | ||
234 | .set_runlist_interleave = gk20a_fifo_set_runlist_interleave, | ||
235 | .tsg_set_timeslice = gk20a_fifo_tsg_set_timeslice, | ||
236 | .force_reset_ch = gk20a_fifo_force_reset_ch, | ||
237 | .engine_enum_from_type = gk20a_fifo_engine_enum_from_type, | ||
238 | .device_info_data_parse = gm20b_device_info_data_parse, | ||
239 | .eng_runlist_base_size = fifo_eng_runlist_base__size_1_v, | ||
240 | .init_engine_info = gk20a_fifo_init_engine_info, | ||
241 | .runlist_entry_size = ram_rl_entry_size_v, | ||
242 | .get_tsg_runlist_entry = gk20a_get_tsg_runlist_entry, | ||
243 | .get_ch_runlist_entry = gk20a_get_ch_runlist_entry, | ||
244 | .is_fault_engine_subid_gpc = gk20a_is_fault_engine_subid_gpc, | ||
245 | .dump_pbdma_status = gk20a_dump_pbdma_status, | ||
246 | .dump_eng_status = gk20a_dump_eng_status, | ||
247 | .dump_channel_status_ramfc = gk20a_dump_channel_status_ramfc, | ||
248 | .intr_0_error_mask = gk20a_fifo_intr_0_error_mask, | ||
249 | .is_preempt_pending = gk20a_fifo_is_preempt_pending, | ||
250 | .init_pbdma_intr_descs = gm20b_fifo_init_pbdma_intr_descs, | ||
251 | .reset_enable_hw = gk20a_init_fifo_reset_enable_hw, | ||
252 | .teardown_ch_tsg = gk20a_fifo_teardown_ch_tsg, | ||
253 | .handle_sched_error = gk20a_fifo_handle_sched_error, | ||
254 | .handle_pbdma_intr_0 = gk20a_fifo_handle_pbdma_intr_0, | ||
255 | .handle_pbdma_intr_1 = gk20a_fifo_handle_pbdma_intr_1, | ||
256 | .tsg_bind_channel = gk20a_tsg_bind_channel, | ||
257 | .tsg_unbind_channel = gk20a_tsg_unbind_channel, | ||
258 | #ifdef CONFIG_TEGRA_GK20A_NVHOST | ||
259 | .alloc_syncpt_buf = gk20a_fifo_alloc_syncpt_buf, | ||
260 | .free_syncpt_buf = gk20a_fifo_free_syncpt_buf, | ||
261 | .add_syncpt_wait_cmd = gk20a_fifo_add_syncpt_wait_cmd, | ||
262 | .get_syncpt_wait_cmd_size = gk20a_fifo_get_syncpt_wait_cmd_size, | ||
263 | .add_syncpt_incr_cmd = gk20a_fifo_add_syncpt_incr_cmd, | ||
264 | .get_syncpt_incr_cmd_size = gk20a_fifo_get_syncpt_incr_cmd_size, | ||
265 | #endif | ||
266 | }, | ||
205 | .mc = { | 267 | .mc = { |
206 | .intr_enable = mc_gk20a_intr_enable, | 268 | .intr_enable = mc_gk20a_intr_enable, |
207 | .intr_unit_config = mc_gk20a_intr_unit_config, | 269 | .intr_unit_config = mc_gk20a_intr_unit_config, |
@@ -271,6 +333,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
271 | 333 | ||
272 | gops->ltc = gm20b_ops.ltc; | 334 | gops->ltc = gm20b_ops.ltc; |
273 | gops->clock_gating = gm20b_ops.clock_gating; | 335 | gops->clock_gating = gm20b_ops.clock_gating; |
336 | gops->fifo = gm20b_ops.fifo; | ||
274 | gops->mc = gm20b_ops.mc; | 337 | gops->mc = gm20b_ops.mc; |
275 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; | 338 | gops->dbg_session_ops = gm20b_ops.dbg_session_ops; |
276 | gops->debug = gm20b_ops.debug; | 339 | gops->debug = gm20b_ops.debug; |
@@ -320,7 +383,6 @@ int gm20b_init_hal(struct gk20a *g) | |||
320 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; | 383 | g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; |
321 | gm20b_init_gr(gops); | 384 | gm20b_init_gr(gops); |
322 | gm20b_init_fb(gops); | 385 | gm20b_init_fb(gops); |
323 | gm20b_init_fifo(gops); | ||
324 | gm20b_init_ce2(gops); | 386 | gm20b_init_ce2(gops); |
325 | gm20b_init_gr_ctx(gops); | 387 | gm20b_init_gr_ctx(gops); |
326 | gm20b_init_mm(gops); | 388 | gm20b_init_mm(gops); |
@@ -328,7 +390,7 @@ int gm20b_init_hal(struct gk20a *g) | |||
328 | gm20b_init_clk_ops(gops); | 390 | gm20b_init_clk_ops(gops); |
329 | gm20b_init_regops(gops); | 391 | gm20b_init_regops(gops); |
330 | gm20b_init_therm_ops(gops); | 392 | gm20b_init_therm_ops(gops); |
331 | gk20a_init_tsg_ops(gops); | 393 | |
332 | g->name = "gm20b"; | 394 | g->name = "gm20b"; |
333 | 395 | ||
334 | c->twod_class = FERMI_TWOD_A; | 396 | c->twod_class = FERMI_TWOD_A; |