summaryrefslogtreecommitdiffstats
path: root/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
diff options
context:
space:
mode:
authorSunny He <suhe@nvidia.com>2017-08-17 19:11:34 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2017-08-24 12:34:43 -0400
commit4b5b67d6d83430d8d670660b1dfc9cf024d60d88 (patch)
tree541a421438fe849ee4b1ab9e6bdfa9e8b6ee4485 /drivers/gpu/nvgpu/gm20b/hal_gm20b.c
parent82ba1277f3da7379ed6b8288c04bb91db008549c (diff)
gpu: nvgpu: Reorg gr HAL initialization
Reorganize HAL initialization to remove inheritance and construct the gpu_ops struct at compile time. This patch only covers the gr sub-module of the gpu_ops struct. Perform HAL function assignments in hal_gxxxx.c through the population of a chip-specific copy of gpu_ops. Jira NVGPU-74 Change-Id: Ie37638f442fd68aca8a7ade5f297118447bdc91e Signed-off-by: Sunny He <suhe@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1542989 Reviewed-by: Automatic_Commit_Validation_User Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> Reviewed-by: svccoveritychecker <svccoveritychecker@nvidia.com> Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hal_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c120
1 files changed, 118 insertions, 2 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index aa953ca5..b77f10d2 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -27,6 +27,7 @@
27#include "gk20a/priv_ring_gk20a.h" 27#include "gk20a/priv_ring_gk20a.h"
28#include "gk20a/regops_gk20a.h" 28#include "gk20a/regops_gk20a.h"
29#include "gk20a/pmu_gk20a.h" 29#include "gk20a/pmu_gk20a.h"
30#include "gk20a/gr_gk20a.h"
30 31
31#include "ltc_gm20b.h" 32#include "ltc_gm20b.h"
32#include "gr_gm20b.h" 33#include "gr_gm20b.h"
@@ -170,6 +171,118 @@ static const struct gpu_ops gm20b_ops = {
170 .isr_stall = gk20a_ce2_isr, 171 .isr_stall = gk20a_ce2_isr,
171 .isr_nonstall = gk20a_ce2_nonstall_isr, 172 .isr_nonstall = gk20a_ce2_nonstall_isr,
172 }, 173 },
174 .gr = {
175 .init_gpc_mmu = gr_gm20b_init_gpc_mmu,
176 .bundle_cb_defaults = gr_gm20b_bundle_cb_defaults,
177 .cb_size_default = gr_gm20b_cb_size_default,
178 .calc_global_ctx_buffer_size =
179 gr_gm20b_calc_global_ctx_buffer_size,
180 .commit_global_attrib_cb = gr_gm20b_commit_global_attrib_cb,
181 .commit_global_bundle_cb = gr_gm20b_commit_global_bundle_cb,
182 .commit_global_cb_manager = gr_gm20b_commit_global_cb_manager,
183 .commit_global_pagepool = gr_gm20b_commit_global_pagepool,
184 .handle_sw_method = gr_gm20b_handle_sw_method,
185 .set_alpha_circular_buffer_size =
186 gr_gm20b_set_alpha_circular_buffer_size,
187 .set_circular_buffer_size = gr_gm20b_set_circular_buffer_size,
188 .enable_hww_exceptions = gr_gk20a_enable_hww_exceptions,
189 .is_valid_class = gr_gm20b_is_valid_class,
190 .is_valid_gfx_class = gr_gm20b_is_valid_gfx_class,
191 .is_valid_compute_class = gr_gm20b_is_valid_compute_class,
192 .get_sm_dsm_perf_regs = gr_gm20b_get_sm_dsm_perf_regs,
193 .get_sm_dsm_perf_ctrl_regs = gr_gm20b_get_sm_dsm_perf_ctrl_regs,
194 .init_fs_state = gr_gm20b_init_fs_state,
195 .set_hww_esr_report_mask = gr_gm20b_set_hww_esr_report_mask,
196 .falcon_load_ucode = gr_gm20b_load_ctxsw_ucode_segments,
197 .load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode,
198 .set_gpc_tpc_mask = gr_gm20b_set_gpc_tpc_mask,
199 .get_gpc_tpc_mask = gr_gm20b_get_gpc_tpc_mask,
200 .free_channel_ctx = gk20a_free_channel_ctx,
201 .alloc_obj_ctx = gk20a_alloc_obj_ctx,
202 .bind_ctxsw_zcull = gr_gk20a_bind_ctxsw_zcull,
203 .get_zcull_info = gr_gk20a_get_zcull_info,
204 .is_tpc_addr = gr_gm20b_is_tpc_addr,
205 .get_tpc_num = gr_gm20b_get_tpc_num,
206 .detect_sm_arch = gr_gm20b_detect_sm_arch,
207 .add_zbc_color = gr_gk20a_add_zbc_color,
208 .add_zbc_depth = gr_gk20a_add_zbc_depth,
209 .zbc_set_table = gk20a_gr_zbc_set_table,
210 .zbc_query_table = gr_gk20a_query_zbc,
211 .pmu_save_zbc = gk20a_pmu_save_zbc,
212 .add_zbc = gr_gk20a_add_zbc,
213 .pagepool_default_size = gr_gm20b_pagepool_default_size,
214 .init_ctx_state = gr_gk20a_init_ctx_state,
215 .alloc_gr_ctx = gr_gm20b_alloc_gr_ctx,
216 .free_gr_ctx = gr_gk20a_free_gr_ctx,
217 .update_ctxsw_preemption_mode =
218 gr_gm20b_update_ctxsw_preemption_mode,
219 .dump_gr_regs = gr_gm20b_dump_gr_status_regs,
220 .update_pc_sampling = gr_gm20b_update_pc_sampling,
221 .get_fbp_en_mask = gr_gm20b_get_fbp_en_mask,
222 .get_max_ltc_per_fbp = gr_gm20b_get_max_ltc_per_fbp,
223 .get_max_lts_per_ltc = gr_gm20b_get_max_lts_per_ltc,
224 .get_rop_l2_en_mask = gr_gm20b_rop_l2_en_mask,
225 .get_max_fbps_count = gr_gm20b_get_max_fbps_count,
226 .init_sm_dsm_reg_info = gr_gm20b_init_sm_dsm_reg_info,
227 .wait_empty = gr_gk20a_wait_idle,
228 .init_cyclestats = gr_gm20b_init_cyclestats,
229 .set_sm_debug_mode = gr_gk20a_set_sm_debug_mode,
230 .enable_cde_in_fecs = gr_gm20b_enable_cde_in_fecs,
231 .bpt_reg_info = gr_gm20b_bpt_reg_info,
232 .get_access_map = gr_gm20b_get_access_map,
233 .handle_fecs_error = gk20a_gr_handle_fecs_error,
234 .handle_sm_exception = gr_gk20a_handle_sm_exception,
235 .handle_tex_exception = gr_gk20a_handle_tex_exception,
236 .enable_gpc_exceptions = gk20a_gr_enable_gpc_exceptions,
237 .enable_exceptions = gk20a_gr_enable_exceptions,
238 .get_lrf_tex_ltc_dram_override = NULL,
239 .update_smpc_ctxsw_mode = gr_gk20a_update_smpc_ctxsw_mode,
240 .update_hwpm_ctxsw_mode = gr_gk20a_update_hwpm_ctxsw_mode,
241 .record_sm_error_state = gm20b_gr_record_sm_error_state,
242 .update_sm_error_state = gm20b_gr_update_sm_error_state,
243 .clear_sm_error_state = gm20b_gr_clear_sm_error_state,
244 .suspend_contexts = gr_gk20a_suspend_contexts,
245 .resume_contexts = gr_gk20a_resume_contexts,
246 .get_preemption_mode_flags = gr_gm20b_get_preemption_mode_flags,
247 .fuse_override = gm20b_gr_fuse_override,
248 .init_sm_id_table = gr_gk20a_init_sm_id_table,
249 .load_smid_config = gr_gm20b_load_smid_config,
250 .program_sm_id_numbering = gr_gm20b_program_sm_id_numbering,
251 .is_ltcs_ltss_addr = gr_gm20b_is_ltcs_ltss_addr,
252 .is_ltcn_ltss_addr = gr_gm20b_is_ltcn_ltss_addr,
253 .split_lts_broadcast_addr = gr_gm20b_split_lts_broadcast_addr,
254 .split_ltc_broadcast_addr = gr_gm20b_split_ltc_broadcast_addr,
255 .setup_rop_mapping = gr_gk20a_setup_rop_mapping,
256 .program_zcull_mapping = gr_gk20a_program_zcull_mapping,
257 .commit_global_timeslice = gr_gk20a_commit_global_timeslice,
258 .commit_inst = gr_gk20a_commit_inst,
259 .write_zcull_ptr = gr_gk20a_write_zcull_ptr,
260 .write_pm_ptr = gr_gk20a_write_pm_ptr,
261 .init_elcg_mode = gr_gk20a_init_elcg_mode,
262 .load_tpc_mask = gr_gm20b_load_tpc_mask,
263 .inval_icache = gr_gk20a_inval_icache,
264 .trigger_suspend = gr_gk20a_trigger_suspend,
265 .wait_for_pause = gr_gk20a_wait_for_pause,
266 .resume_from_pause = gr_gk20a_resume_from_pause,
267 .clear_sm_errors = gr_gk20a_clear_sm_errors,
268 .tpc_enabled_exceptions = gr_gk20a_tpc_enabled_exceptions,
269 .get_esr_sm_sel = gk20a_gr_get_esr_sm_sel,
270 .sm_debugger_attached = gk20a_gr_sm_debugger_attached,
271 .suspend_single_sm = gk20a_gr_suspend_single_sm,
272 .suspend_all_sms = gk20a_gr_suspend_all_sms,
273 .resume_single_sm = gk20a_gr_resume_single_sm,
274 .resume_all_sms = gk20a_gr_resume_all_sms,
275 .get_sm_hww_warp_esr = gk20a_gr_get_sm_hww_warp_esr,
276 .get_sm_hww_global_esr = gk20a_gr_get_sm_hww_global_esr,
277 .get_sm_no_lock_down_hww_global_esr_mask =
278 gk20a_gr_get_sm_no_lock_down_hww_global_esr_mask,
279 .lock_down_sm = gk20a_gr_lock_down_sm,
280 .wait_for_sm_lock_down = gk20a_gr_wait_for_sm_lock_down,
281 .clear_sm_hww = gm20b_gr_clear_sm_hww,
282 .init_ovr_sm_dsm_perf = gk20a_gr_init_ovr_sm_dsm_perf,
283 .get_ovr_perf_regs = gk20a_gr_get_ovr_perf_regs,
284 .disable_rd_coalesce = gm20a_gr_disable_rd_coalesce,
285 },
173 .fb = { 286 .fb = {
174 .reset = fb_gk20a_reset, 287 .reset = fb_gk20a_reset,
175 .init_hw = gk20a_fb_init_hw, 288 .init_hw = gk20a_fb_init_hw,
@@ -448,6 +561,7 @@ int gm20b_init_hal(struct gk20a *g)
448 561
449 gops->ltc = gm20b_ops.ltc; 562 gops->ltc = gm20b_ops.ltc;
450 gops->ce2 = gm20b_ops.ce2; 563 gops->ce2 = gm20b_ops.ce2;
564 gops->gr = gm20b_ops.gr;
451 gops->fb = gm20b_ops.fb; 565 gops->fb = gm20b_ops.fb;
452 gops->clock_gating = gm20b_ops.clock_gating; 566 gops->clock_gating = gm20b_ops.clock_gating;
453 gops->fifo = gm20b_ops.fifo; 567 gops->fifo = gm20b_ops.fifo;
@@ -538,6 +652,8 @@ int gm20b_init_hal(struct gk20a *g)
538 652
539 gops->pmu.init_wpr_region = gm20b_pmu_init_acr; 653 gops->pmu.init_wpr_region = gm20b_pmu_init_acr;
540 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode; 654 gops->pmu.load_lsfalcon_ucode = gm20b_load_falcon_ucode;
655
656 gops->gr.load_ctxsw_ucode = gr_gm20b_load_ctxsw_ucode;
541 } else { 657 } else {
542 /* Inherit from gk20a */ 658 /* Inherit from gk20a */
543 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported; 659 gops->pmu.is_pmu_supported = gk20a_is_pmu_supported;
@@ -547,14 +663,14 @@ int gm20b_init_hal(struct gk20a *g)
547 663
548 gops->pmu.load_lsfalcon_ucode = NULL; 664 gops->pmu.load_lsfalcon_ucode = NULL;
549 gops->pmu.init_wpr_region = NULL; 665 gops->pmu.init_wpr_region = NULL;
666
667 gops->gr.load_ctxsw_ucode = gr_gk20a_load_ctxsw_ucode;
550 } 668 }
551 669
552 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false); 670 __nvgpu_set_enabled(g, NVGPU_PMU_FECS_BOOTSTRAP_DONE, false);
553 g->pmu_lsf_pmu_wpr_init_done = 0; 671 g->pmu_lsf_pmu_wpr_init_done = 0;
554 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT; 672 g->bootstrap_owner = LSF_BOOTSTRAP_OWNER_DEFAULT;
555 673
556 gm20b_init_gr(g);
557
558 gm20b_init_uncompressed_kind_map(); 674 gm20b_init_uncompressed_kind_map();
559 gm20b_init_kind_attr(); 675 gm20b_init_kind_attr();
560 676