gpu: nvgpu: add HALs to allocate/map/commit global context buffers

Add below new HALs to allocate/map/commit global context buffers
gops.gr.alloc_global_ctx_buffers()
gops.gr.map_global_ctx_buffers()
gops.gr.commit_global_ctx_buffers()

Set these HALs for all the supported GPUs

We right now re-use below APIs to set these HALs
gr_gk20a_alloc_global_ctx_buffers()
gr_gk20a_map_global_ctx_buffers()
gr_gk20a_commit_global_ctx_buffers()

Jira NVGPUT-27

Change-Id: I975a54e8d1716af057f982d543787748d35a256e
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1743362
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 3 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 9f93d0eb..715946be 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -327,6 +327,9 @@ static const struct gpu_ops gm20b_ops = {
                         gr_gm20b_get_pmm_per_chiplet_offset,
                 .split_fbpa_broadcast_addr = gr_gk20a_split_fbpa_broadcast_addr,
                 .fecs_ctxsw_mailbox_size = gr_fecs_ctxsw_mailbox__size_1_v,
+                .alloc_global_ctx_buffers = gr_gk20a_alloc_global_ctx_buffers,
+                .map_global_ctx_buffers = gr_gk20a_map_global_ctx_buffers,
+                .commit_global_ctx_buffers = gr_gk20a_commit_global_ctx_buffers,
         },
         .fb = {
                 .reset = fb_gk20a_reset,