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authorDeepak Nibade <dnibade@nvidia.com>2018-04-06 08:56:34 -0400
committermobile promotions <svcmobile_promotions@nvidia.com>2018-04-10 14:23:03 -0400
commit4314771142e0b68810b8fa86ec45b6f6b4e24651 (patch)
tree32c1916385ecdb63073400e07e85266df5f8d412 /drivers/gpu/nvgpu/gm20b/hal_gm20b.c
parente1200259ba3ad4ae416990b2f2abccb94565430f (diff)
gpu: nvgpu: add broadcast address decode support for volta
With Volta we have more number of broadcast registers than previous chips and we don't decode them right now in gr_gk20a_decode_priv_addr() Add a new GR HAL decode_priv_addr() and set gr_gk20a_decode_priv_addr() for all previous chips Add and use gr_gv11b_decode_priv_addr() for Volta gr_gv11b_decode_priv_addr() will decode all the broadcast registers and set the broadcast flags apporiately Define below new broadcast types PRI_BROADCAST_FLAGS_PMMGPC PRI_BROADCAST_FLAGS_PMM_GPCS PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCA PRI_BROADCAST_FLAGS_PMM_GPCGS_GPCTPCB PRI_BROADCAST_FLAGS_PMMFBP PRI_BROADCAST_FLAGS_PMM_FBPS PRI_BROADCAST_FLAGS_PMM_FBPGS_LTC PRI_BROADCAST_FLAGS_PMM_FBPGS_ROP Bug 200398811 Jira NVGPU-556 Change-Id: Ic673b357a75b6af3d24a4c16bb5b6bc15974d5b7 Signed-off-by: Deepak Nibade <dnibade@nvidia.com> Reviewed-on: https://git-master.nvidia.com/r/1690026 Reviewed-by: svc-mobile-coverity <svc-mobile-coverity@nvidia.com> GVS: Gerrit_Virtual_Submit Reviewed-by: Terje Bergstrom <tbergstrom@nvidia.com> Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com> Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/hal_gm20b.c')
-rw-r--r--drivers/gpu/nvgpu/gm20b/hal_gm20b.c1
1 files changed, 1 insertions, 0 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
index 82e8826e..65e75374 100644
--- a/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/hal_gm20b.c
@@ -320,6 +320,7 @@ static const struct gpu_ops gm20b_ops = {
320 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending, 320 .handle_semaphore_pending = gk20a_gr_handle_semaphore_pending,
321 .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa, 321 .add_ctxsw_reg_pm_fbpa = gr_gk20a_add_ctxsw_reg_pm_fbpa,
322 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma, 322 .add_ctxsw_reg_perf_pma = gr_gk20a_add_ctxsw_reg_perf_pma,
323 .decode_priv_addr = gr_gk20a_decode_priv_addr,
323 }, 324 },
324 .fb = { 325 .fb = {
325 .reset = fb_gk20a_reset, 326 .reset = fb_gk20a_reset,