gpu: nvgpu: support config of TPC FUSE dynamically

Follow steps below to config active TPC number:
echo 1 > /sys/devices/platform/host1x/gpu.0/force_idle
echo 0x1/0x2/0x3 > /sys/devices/platform/host1x/gpu.0/tpc_fs_mask
echo 0 > /sys/devices/platform/host1x/gpu.0/force_idle

where,
0x1 : disable TPC1
0x2 : disable TPC0
0x3 : both TPCs active

Also, add API set_gpc_tpc_mask to update the TPCs and call this
API after update to sysfs "tpc_fs_mask"
Once fuses are updated for new TPC settings, we need to
reconfigure GR and golden_image. Hence disable gr->sw_ready
and golden_image_initialized flags.

Also, initialize gr->tpc_count = 0 each time in
gr_gk20a_init_gr_config(), otherwise it goes on adding tpc count

Bug 1513685

Change-Id: Ib50bafef08664262f8426ac0d6cbad74b32c5909
Signed-off-by: Kevin Huang <kevinh@nvidia.com>
Signed-off-by: Deepak Nibade <dnibade@nvidia.com>
Reviewed-on: http://git-master/r/552606
Reviewed-by: Sachin Nikam <snikam@nvidia.com>

1 files changed, 11 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
index 470e5bae..fd109eec 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h
@@ -25,6 +25,17 @@ enum {
         MAXWELL_CHANNEL_GPFIFO_A= 0xB06F,
 };
 
+#define tegra_clk_writel(value, offset) \
+        writel(value, IO_ADDRESS(0x60006000 + offset))
+
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0               0x48
+#define CLK_RST_CONTROLLER_MISC_CLK_ENB_0_ALL_VISIBLE   BIT(28)
+
+#define FUSE_FUSEBYPASS_0                               0x24
+#define FUSE_WRITE_ACCESS_SW_0                          0x30
+#define FUSE_OPT_GPU_TPC0_DISABLE_0                     0x30C
+#define FUSE_OPT_GPU_TPC1_DISABLE_0                     0x33C
+
 #define NVB197_SET_ALPHA_CIRCULAR_BUFFER_SIZE   0x02dc
 #define NVB197_SET_CIRCULAR_BUFFER_SIZE         0x1280
 #define NVB197_SET_SHADER_EXCEPTIONS            0x1528