diff options
author | Thomas Fleury <tfleury@nvidia.com> | 2019-04-30 20:19:51 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2020-01-30 02:41:45 -0500 |
commit | dc281d6a9ebadaeb66dab092b40b7d6f4559ee39 (patch) | |
tree | cbe2c286c1549c2824eade89a25c033a86a7dd6e /drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |
parent | 6e91ecaae77d769955e5e1f34ded90c064e9c245 (diff) |
gpu: nvgpu: add SET_CTX_MMU_DEBUG_MODE ioctl
Added NVGPU_DBG_GPU_IOCTL_SET_CTX_MMU_DEBUG_MODE ioctl to set MMU
debug mode for a given context.
Added gr.set_mmu_debug_mode HAL to change NV_PGPC_PRI_MMU_DEBUG_CTRL
for a given channel. HAL implementation for native case is
gm20b_gr_set_mmu_debug_mode. It internally uses regops, which directly
writes to the register if the context is resident, or writes to
gr context otherwise.
Added NVGPU_SUPPORT_SET_CTX_MMU_DEBUG_MODE to enable the feature.
NV_PGPC_PRI_MMU_DEBUG_CTRL has to be context switched in FECS ucode,
so the feature is only enabled on TU104 for now.
Bug 2515097
But 2713590
Change-Id: Ib4efaf06fc47a8539b4474f94c68c20ce225263f
Signed-off-by: Thomas Fleury <tfleury@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/2110720
(cherry-picked from commit af2ccb811d3de06f052b1dee39bd9ffa863ac8ce)
Reviewed-on: https://git-master.nvidia.com/r/c/linux-nvgpu/+/2208767
Reviewed-by: Kajetan Dutka <kdutka@nvidia.com>
Reviewed-by: Alex Waterman <alexw@nvidia.com>
Reviewed-by: Winnie Hsu <whsu@nvidia.com>
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
GVS: Gerrit_Virtual_Submit
Tested-by: Kajetan Dutka <kdutka@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 4 |
1 files changed, 3 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index 084b6157..81916c05 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -1,7 +1,7 @@ | |||
1 | /* | 1 | /* |
2 | * GM20B GPC MMU | 2 | * GM20B GPC MMU |
3 | * | 3 | * |
4 | * Copyright (c) 2014-2018, NVIDIA CORPORATION. All rights reserved. | 4 | * Copyright (c) 2014-2020, NVIDIA CORPORATION. All rights reserved. |
5 | * | 5 | * |
6 | * Permission is hereby granted, free of charge, to any person obtaining a | 6 | * Permission is hereby granted, free of charge, to any person obtaining a |
7 | * copy of this software and associated documentation files (the "Software"), | 7 | * copy of this software and associated documentation files (the "Software"), |
@@ -125,5 +125,7 @@ int gr_gm20b_get_preemption_mode_flags(struct gk20a *g, | |||
125 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, | 125 | void gm20b_gr_clear_sm_hww(struct gk20a *g, u32 gpc, u32 tpc, u32 sm, |
126 | u32 global_esr); | 126 | u32 global_esr); |
127 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); | 127 | u32 gr_gm20b_get_pmm_per_chiplet_offset(void); |
128 | int gm20b_gr_set_mmu_debug_mode(struct gk20a *g, | ||
129 | struct channel_gk20a *ch, bool enable); | ||
128 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); | 130 | void gm20b_gr_set_debug_mode(struct gk20a *g, bool enable); |
129 | #endif /* NVGPU_GM20B_GR_GM20B_H */ | 131 | #endif /* NVGPU_GM20B_GR_GM20B_H */ |