diff options
author | Richard Zhao <rizhao@nvidia.com> | 2018-06-06 23:46:03 -0400 |
---|---|---|
committer | Tejal Kudav <tkudav@nvidia.com> | 2018-06-14 09:44:08 -0400 |
commit | 6a46965eb3b7b657c089142579ab20d6efefc0fc (patch) | |
tree | 60aa4098d4b50af9db21e316098cfbe35c9a4797 /drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |
parent | 7a5d498a711833990a9d8fc3f5d3f3e26bee301c (diff) |
gpu: nvgpu: correct calculation of sm_id for .record_sm_error_state
Starting with Volta, one TPC could have more than 1 SMs. So
.record_sm_error_state needs to have sm number as parameter.
Logic tpc id should be read from gr_gpc0_gpm_pd_sm_id_r.
Let the function return logical sm_id. RM server will need it to nofify
client.
Jira EVLR-2643
Bug 200405202
Change-Id: Iffaff05b89b1c5058616b8a6bf50dd73bd4e52f6
Signed-off-by: Richard Zhao <rizhao@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1742165
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.h')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.h | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h index ff32d8ff..5c82fd65 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.h +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.h | |||
@@ -116,7 +116,7 @@ void gr_gm20b_bpt_reg_info(struct gk20a *g, struct nvgpu_warpstate *w_state); | |||
116 | void gr_gm20b_get_access_map(struct gk20a *g, | 116 | void gr_gm20b_get_access_map(struct gk20a *g, |
117 | u32 **whitelist, int *num_entries); | 117 | u32 **whitelist, int *num_entries); |
118 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, | 118 | int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, |
119 | u32 tpc, struct channel_gk20a *fault_ch); | 119 | u32 tpc, u32 sm, struct channel_gk20a *fault_ch); |
120 | int gm20b_gr_update_sm_error_state(struct gk20a *g, | 120 | int gm20b_gr_update_sm_error_state(struct gk20a *g, |
121 | struct channel_gk20a *ch, u32 sm_id, | 121 | struct channel_gk20a *ch, u32 sm_id, |
122 | struct nvgpu_gr_sm_error_state *sm_error_state); | 122 | struct nvgpu_gr_sm_error_state *sm_error_state); |