gpu: nvgpu: SM/TEX exception handling support

Add TEX exception handling support. Also make SM exception handler into
a function pointer, which should allow different chips to implement
their own SM exception handling routine.

Bug 1635727
Bug 1637486

Change-Id: I429905726c1840c11e83780843d82729495dc6a5
Signed-off-by: Adeel Raza <araza@nvidia.com>
Reviewed-on: http://git-master/r/935329

1 files changed, 2 insertions, 0 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index a80cef8f..ab1b166d 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1229,4 +1229,6 @@ void gm20b_init_gr(struct gpu_ops *gops)
         gops->gr.get_access_map = gr_gm20b_get_access_map;
         gops->gr.handle_fecs_error = gk20a_gr_handle_fecs_error;
         gops->gr.mask_hww_warp_esr = gk20a_mask_hww_warp_esr;
+        gops->gr.handle_sm_exception = gr_gk20a_handle_sm_exception;
+        gops->gr.handle_tex_exception = gr_gk20a_handle_tex_exception;
 }