diff options
author | Sunny He <suhe@nvidia.com> | 2017-06-28 17:16:53 -0400 |
---|---|---|
committer | mobile promotions <svcmobile_promotions@nvidia.com> | 2017-07-26 05:44:23 -0400 |
commit | de3ad1a94974b08268a485136f04b8e436ef2579 (patch) | |
tree | 15910cd769e91f6600fef0546b501faf65e1fa50 /drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |
parent | 92f6eb016cc759b24e249ed6c17cff537cc35db7 (diff) |
gpu: nvgpu: Remove securegpccs flag from gpu_ops
Replace securegpccs boolean flag in gpu_ops with entry in
common flag system.
The new common flag is NVGPU_SEC_SECUREGPCCS
Jira NVGPU-74
Change-Id: I46430f95063f617531cf0e5aba472051b41f4a9d
Signed-off-by: Sunny He <suhe@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1514060
Reviewed-by: Automatic_Commit_Validation_User
Reviewed-by: Alex Waterman <alexw@nvidia.com>
GVS: Gerrit_Virtual_Submit
Reviewed-by: Vijayakumar Subbu <vsubbu@nvidia.com>
Diffstat (limited to 'drivers/gpu/nvgpu/gm20b/gr_gm20b.c')
-rw-r--r-- | drivers/gpu/nvgpu/gm20b/gr_gm20b.c | 6 |
1 files changed, 3 insertions, 3 deletions
diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c index bd9b627f..5d9cc32c 100644 --- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c +++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c | |||
@@ -758,7 +758,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
758 | g->ops.pmu.lsfloadedfalconid = 0; | 758 | g->ops.pmu.lsfloadedfalconid = 0; |
759 | if (g->ops.pmu.fecsbootstrapdone) { | 759 | if (g->ops.pmu.fecsbootstrapdone) { |
760 | /* this must be recovery so bootstrap fecs and gpccs */ | 760 | /* this must be recovery so bootstrap fecs and gpccs */ |
761 | if (!g->ops.securegpccs) { | 761 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
762 | gr_gm20b_load_gpccs_with_bootloader(g); | 762 | gr_gm20b_load_gpccs_with_bootloader(g); |
763 | err = g->ops.pmu.load_lsfalcon_ucode(g, | 763 | err = g->ops.pmu.load_lsfalcon_ucode(g, |
764 | (1 << LSF_FALCON_ID_FECS)); | 764 | (1 << LSF_FALCON_ID_FECS)); |
@@ -777,7 +777,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
777 | } else { | 777 | } else { |
778 | /* cold boot or rg exit */ | 778 | /* cold boot or rg exit */ |
779 | g->ops.pmu.fecsbootstrapdone = true; | 779 | g->ops.pmu.fecsbootstrapdone = true; |
780 | if (!g->ops.securegpccs) { | 780 | if (!nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
781 | gr_gm20b_load_gpccs_with_bootloader(g); | 781 | gr_gm20b_load_gpccs_with_bootloader(g); |
782 | } else { | 782 | } else { |
783 | /* bind WPR VA inst block */ | 783 | /* bind WPR VA inst block */ |
@@ -797,7 +797,7 @@ static int gr_gm20b_load_ctxsw_ucode(struct gk20a *g) | |||
797 | } | 797 | } |
798 | 798 | ||
799 | /*start gpccs */ | 799 | /*start gpccs */ |
800 | if (g->ops.securegpccs) { | 800 | if (nvgpu_is_enabled(g, NVGPU_SEC_SECUREGPCCS)) { |
801 | gk20a_writel(g, reg_offset + | 801 | gk20a_writel(g, reg_offset + |
802 | gr_fecs_cpuctl_alias_r(), | 802 | gr_fecs_cpuctl_alias_r(), |
803 | gr_gpccs_cpuctl_startcpu_f(1)); | 803 | gr_gpccs_cpuctl_startcpu_f(1)); |