gpu: nvgpu: ctx_patch_write fixes

- Add update_patch_count parameter to ctx_patch_write_begin/end functions
  If True, the main_image_patch_count register will be updated. Previously,
  the patch count would be updated if the cpu_va for the graphics context
  was non-NULL, but this only works for sysmem (cpu_va is always 0 for vidmem)

- Remove unused patch parameter for the commit_global_timeslice functions

JIRA ESRM-74
Bug 2012077

Change-Id: I35d0a9eb48669a227833bba1d2e63e9fe8fd8aa9
Signed-off-by: Peter Daifuku <pdaifuku@nvidia.com>
Reviewed-on: https://git-master.nvidia.com/r/1594790
Reviewed-by: mobile promotions <svcmobile_promotions@nvidia.com>
Tested-by: mobile promotions <svcmobile_promotions@nvidia.com>

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 4c49f734..c692d975 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1339,7 +1339,7 @@ int gm20b_gr_update_sm_error_state(struct gk20a *g,
                 gk20a_writel(g, gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset,
                                 gr->sm_error_states[sm_id].hww_warp_esr_report_mask);
         } else {
-                err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx);
+                err = gr_gk20a_ctx_patch_write_begin(g, ch_ctx, false);
                 if (err)
                         goto enable_ctxsw;
 
@@ -1352,7 +1352,7 @@ int gm20b_gr_update_sm_error_state(struct gk20a *g,
                                 gr->sm_error_states[sm_id].hww_warp_esr_report_mask,
                                 true);
 
-                gr_gk20a_ctx_patch_write_end(g, ch_ctx);
+                gr_gk20a_ctx_patch_write_end(g, ch_ctx, false);
         }
 
 enable_ctxsw: