gpu: nvgpu: Fix unicast register accesses for SM

In two places we used broadcast register as base, but added the
unicast offset to it. This causes the write to go well beyond
valid register range.

Change the broadcast base to use unicast base instead in sequence
to resume a single SM and to record error state of SM.

Bug 200256272

Change-Id: I4ca9af2bb5877dba20ab96575f5094d42949c9e2
Signed-off-by: Terje Bergstrom <tbergstrom@nvidia.com>
(cherry-picked from commit 04177b3414535ce5092c8baeae29883bada9d36c)
Reviewed-on: http://git-master/r/1306331
Reviewed-by: Automatic_Commit_Validation_User

1 files changed, 2 insertions, 2 deletions

diff --git a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
index 0e0d3f62..0375d71f 100644
--- a/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
+++ b/drivers/gpu/nvgpu/gm20b/gr_gm20b.c
@@ -1259,9 +1259,9 @@ static int gm20b_gr_record_sm_error_state(struct gk20a *g, u32 gpc, u32 tpc)
         gr->sm_error_states[sm_id].hww_warp_esr_pc = gk20a_readl(g,
                         gr_gpc0_tpc0_sm_hww_warp_esr_pc_r() + offset);
         gr->sm_error_states[sm_id].hww_global_esr_report_mask = gk20a_readl(g,
-                       gr_gpcs_tpcs_sm_hww_global_esr_report_mask_r() + offset);
+                       gr_gpc0_tpc0_sm_hww_global_esr_report_mask_r() + offset);
         gr->sm_error_states[sm_id].hww_warp_esr_report_mask = gk20a_readl(g,
-                        gr_gpcs_tpcs_sm_hww_warp_esr_report_mask_r() + offset);
+                        gr_gpc0_tpc0_sm_hww_warp_esr_report_mask_r() + offset);
 
         mutex_unlock(&g->dbg_sessions_lock);